PDF ICS954204 Data sheet ( Hoja de datos )

Número de pieza	ICS954204
Descripción	Programmable Timing Control HubTM for Mobile P4TM Systems
Fabricantes	Integrated Circuit Systems
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No Preview Available ! www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS954204 Programmable Timing Control Hub™ for Mobile P4™ Systems Recommended Application: CK410M Compliant Main Clock with Integrated LCD Spread Spectrum Clock. Output Features: • 2 - 0.7V current-mode differential CPU pairs • 5 - 0.7V current-mode differential SRC pair for SATA and PCI-E • 1 - 0.7V current-mode differential CPU/SRC selectable pair • 4 - PCI (33MHz) • 2 - PCICLK_F, (33MHz) free-running • 1 - USB, 48MHz • 1 - DOT, 96MHz, 0.7V current differential pair • 1 - REF, 14.318MHz • 1 - 0.7V current-mode differential LCD/SRC selectable pair. • PCI outputs cycle-cycle jitter < 500ps • +/- 300ppm frequency accuracy on CPU & SRC clocks • +/- 100ppm frequency accuracy on USB clocks Features/Benefits: • Supports tight ppm accuracy clocks for Serial-ATA and SRC • Supports programmable spread percentage and frequency • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning • Supports undriven differential CPU, SRC pair in PD# for power management. • CLKREQ pins to support SRC power management. Key Specifications: • CPU outputs cycle-cycle jitter < 85ps • SRC outputs cycle-cycle jitter < 125ps Pin Configuration Functionality VDDPCI 1 GND 2 PCICLK3 3 PCICLK4 4 PCICLK5 5 GND 6 VDDPCI 7 ITP_EN/PCICLK_F0 8 SELSRC_LCDCLK#/PCICLK_F1 9 Vtt_PwrGd#/PD 10 VDD48 11 FSLA/USB_48MHz 12 GND 13 DOTT_96MHz 14 DOTC_96MHz 15 FSLB/TEST_MODE 16 LCDCLK_SST/SRCCLKT0 17 LCDCLK_SSC/SRCCLKC0 18 SRCCLKT1 19 SRCCLKC1 20 VDDSRC 21 SRCCLKT2 22 SRCCLKC2 23 SRCCLKT3 24 SRCCLKC3 25 SRCCLKT4_SATA 26 SRCCLKC4_SATA 27 VDDSRC 28 56 PCICLK2 55 PCI/SRC_STOP# CPU SRC PCI FS_C FS_B FS_A MHz MHz MHz REF MHz USB MHz DOT MHz 54 CPU_STOP# 53 FSLC/TEST_SEL 52 REFOUT 51 GND 50 X1 49 X2 48 VDDREF 47 SDATA 46 SCLK 0 0 0 266.67 100.00 33.33 14.318 48.00 96.00 0 0 1 133.33 100.00 33.33 14.318 48.00 96.00 0 1 0 200.00 100.00 33.33 14.318 48.00 96.00 0 1 1 166.67 100.00 33.33 14.318 48.00 96.00 1 0 0 333.33 100.00 33.33 14.318 48.00 96.00 1 0 1 100.00 100.00 33.33 14.318 48.00 96.00 1 1 0 400.00 100.00 33.33 14.318 48.00 96.00 1 1 1 200.00 100.00 33.33 14.318 48.00 96.00 45 GND 44 CPUCLKT0 1. FS_C is a three-level input. Please see VIL_FS and VIH_FS specifications in the 43 CPUCLKC0 Input/Supply/Common Output Parameters Table for correct values. Also refer 42 VDDCPU to the Test Clarification Table. 41 CPUCLKT1 40 CPUCLKC1 39 IREF 38 GNDA 2. FS_B and FS_A are low-threshold inputs. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. 37 VDDA 36 CPUCLKT2_ITP/SRCCLKT7 35 CPUCLKC2_ITP/SRCCLKC7 34 VDDSRC 33 CLKREQA# 32 CLKREQB#* 31 SRCCLKT5 30 SRCCLKC5 29 GND 56-pin TSSOP *100Kohm Pull-Up Resistor 0933D—03/16/05 DataSheet4 U .com 1 page www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS954204 General SMBus serial interface information for the ICS954204 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 (H) • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • Controller (host) sends the data byte count = X • ICS clock will acknowledge • Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit How to Read: • Controller (host) will send start bit. • Controller (host) sends the write address D2 (H) • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • Controller (host) will send a separate start bit. • Controller (host) sends the read address D3 (H) • ICS clock will acknowledge • ICS clock will send the data byte count = X • ICS clock sends Byte N + X -1 • ICS clock sends Byte 0 through byte X • Controller (host) will need to acknowledge each byte • Controllor (host) will send a not acknowledge bit • Controller (host) will send a stop bit Index Block Write Operation Controller (Host) T starT bit ICS (Slave/Receiver) Slave Address D2(H) WR WRite Beginning Byte = N Data Byte Count = X Beginning Byte N ACK ACK ACK ACK Byte N + X - 1 P stoP bit ACK Index Block Read Operation Controller (Host) T starT bit ICS (Slave/Receiver) Slave Address D2(H) WR WRite Beginning Byte = N RT Repeat starT ACK ACK Slave Address D3(H) RD ReaD ACK ACK ACK Data Byte Count = X Beginning Byte N N Not acknowledge P stoP bit Byte N + X - 1 0933D—03/16/05 DataSheet4 U .com 5 5 Page www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS954204 SMBus Table: Output Enable Control Register Byte 0 Pin # Name Bit 7 35, 36 CPUCLK2_ITP/SRCCLK7 Enable Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - 30, 31 26, 27 24, 25 22, 23 19, 20 17, 18 SRCCLK5 Enable SRCCLK4/SATA Enable SRCCLK3 Enable SRCCLK2 Enable SRCCLK1 Enable SRCCLK0 Enable Control Function Output Enable Reserved Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable SMBus Table: PLL1 Spread and Output Enable Control Register Byte 1 Pin # Name Control Function Bit 7 8 PCI_F0 Enable Output Enable Bit 6 14,15 DOT_96MHz Enable Output Enable Bit 5 12 USB_48MHz Enable Output Enable Bit 4 52 REFOUT Enable Output Enable Bit 3 - Reserved Bit 2 41, 40 CPU_1 Enable Output Enable Bit 1 44, 43 CPU_0 Enable Output Enable Bit 0 - Spread Spectrum Mode Spread Control for PLL1 (CPU, SRC, PCIF, PCI) Type RW RW RW RW RW RW RW 0 Disable (HiZ) 1 Enable Disable (HiZ) Disable (HiZ) Disable (HiZ) Disable (HiZ) Disable (HiZ) Disable (HiZ) Enable Enable Enable Enable Enable Enable Type RW RW RW RW RW RW RW 0 Disable Disable (HiZ) Disable Disable 1 Enable Enable Enable Enable Disable (HiZ) Disable (HiZ) Enable Enable SPREAD OFF SPREAD ON SMBus Table: Output Enable Control Register Byte 2 Pin # Name Bit 7 5 PCICLK5 Bit 6 4 PCICLK4 Bit 5 3 PCICLK3 Bit 4 56 PCICLK2 Bit 3 Bit 2 Bit 1 Bit 0 9 PCI_F1 Enable Control Function Output Enable Output Enable Output Enable Output Enable Reserved Reserved Reserved Output Enable SMBus Table: SRC Free-Running Control Register Byte 3 Pin # Name Bit 7 35, 36 SRCCLK7 Bit 6 - Bit 5 30, 31 SRCCLK5 Bit 4 26, 27 SRCCLK4/SATA Bit 3 24, 25 SRCCLK3 Bit 2 22, 23 SRCCLK2 Bit 1 19, 20 SRCCLK1 Bit 0 17, 18 SRCCLK0 Control Function Free-Running Control Reserved Free-Running Control, not affected by PCI/SRC_STOP# Type RW RW RW RW RW Type RW RW RW RW RW RW RW 0 Disable Disable Disable Disable 1 Enable Enable Enable Enable Disable Enable 0 Free-Running 1 Stoppable Free-Running Free-Running Free-Running Free-Running Free-Running Free-Running Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable PWD 1 1 1 1 1 1 1 1 PWD 1 1 1 1 - 1 1 0 PWD 1 1 1 1 1 1 1 1 PWD 0 0 0 0 0 0 0 0 0933D—03/16/05 DataSheet4 U .com 11 11 Page

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