PDF ICS954201 Data sheet ( Hoja de datos )

Número de pieza	ICS954201
Descripción	Programmable Timing Control Hub
Fabricantes	Integrated Circuit Systems
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No Preview Available ! www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS954201 Programmable Timing Control Hub™ for Mobile P4™ Systems Recommended Application: CK410M clock, Intel Yellow Cover part Output Features: • 2 - 0.7V current-mode differential CPU pairs • 7 - 0.7V current-mode differential SRC pair for SATA and PCI-E • 1 - 0.7V current-mode differential CPU/SRC selectable pair • 4 - PCI (33MHz) • 2 - PCICLK_F, (33MHz) free-running • 1 - USB, 48MHz • 1 - DOT, 96MHz, 0.7V current differential pair • 1 - REF, 14.318MHz Features/Benefits: • Supports tight ppm accuracy clocks for Serial-ATA and PCI-Express • Supports spread spectrum modulation, 0 to -0.5% down spread • Supports CPU clocks up to 400MHz • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning • Supports undriven differential CPU, SRC pair in PD# for power management. Key Specifications: • CPU outputs cycle-cycle jitter < 85ps • SRC outputs cycle-cycle jitter < 125ps • PCI outputs cycle-cycle jitter < 500ps • +/- 300ppm frequency accuracy on CPU & SRC clocks • +/- 100ppm frequency accuracy on USB clocks Pin Configuration VDDPCI 1 GND 2 PCICLK3 3 PCICLK4 4 PCICLK5 5 GND 6 VDDPCI 7 ITP_EN/PCICLK_F0 8 PCICLK_F1 9 Vtt_PwrGd#/PD 10 VDD48 11 USB_48MHz/FS_A 12 GND 13 DOTT_96MHz 14 DOTC_96MHz 15 FS_B/TEST_MODE 16 SRCCLKT0 17 SRCCLKC0 18 SRCCLKT1 19 SRCCLKC1 20 VDDSRC 21 SRCCLKT2 22 SRCCLKC2 23 SRCCLKT3 24 SRCCLKC3 25 SRCCLKT4_SATA 26 SRCCLKC4_SATA 27 VDDSRC 28 Functionality 56 PCICLK2 55 PCI/SRC_STOP# 54 CPU_STOP# 53 FS_C/TEST_SEL 52 REFOUT FS_C1 FS_B2 FS_A2 0 00 0 01 0 10 0 11 CPU MHz 266.66 133.33 200.00 166.66 SRC MHz 100.00 100.00 100.00 100.00 PCI REF MHz MHz 33.33 14.318 33.33 14.318 33.33 14.318 33.33 14.318 USB MHz 48.00 48.00 48.00 48.00 DOT MHz 96.00 96.00 96.00 96.00 51 GND 50 X1 49 X2 48 VDDREF 1 0 0 333.33 100.00 33.33 14.318 48.00 96.00 1 0 1 100.00 100.00 33.33 14.318 48.00 96.00 1 1 0 400.00 100.00 33.33 14.318 48.00 96.00 1 11 RESERVED 14.318 48.00 96.00 47 SDATA 46 SCLK 45 GND 44 CPUCLKT0 43 CPUCLKC0 1. FS_C is a three-level input. Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FS_B and FS_A are low-threshold inputs. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. 42 VDDCPU 41 CPUCLKT1 40 CPUCLKC1 39 IREF 38 GNDA 37 VDDA 36 CPUCLKT2_ITP/SRCCLKT7 35 CPUCLKC2_ITP/SRCCLKC7 34 VDDSRC 33 SRCCLKT6 32 SRCCLKC6 31 SRCCLKT5 30 SRCCLKC5 29 GND 56-pin SSOP & TSSOP 0819G—12/06/04 DataSheet4 U .com 1 page www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS954201 General I2C serial interface information for the ICS954201 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 (H) • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • Controller (host) sends the data byte count = X • ICS clock will acknowledge • Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit How to Read: • Controller (host) will send start bit. • Controller (host) sends the write address D2 (H) • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • Controller (host) will send a separate start bit. • Controller (host) sends the read address D3 (H) • ICS clock will acknowledge • ICS clock will send the data byte count = X • ICS clock sends Byte N + X -1 • ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). • Controller (host) will need to acknowledge each byte • Controllor (host) will send a not acknowledge bit • Controller (host) will send a stop bit Index Block Write Operation Controller (Host) T starT bit ICS (Slave/Receiver) Slave Address D2(H) WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK Byte N + X - 1 P stoP bit ACK Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T starT bit Slave Address D2(H) WR WRite ACK Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK ACK ACK Data Byte Count = X Beginning Byte N N Not acknowledge P stoP bit Byte N + X - 1 0819G—12/06/04 DataSheet4 U .com 5 5 Page www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS954201 SMBus Table: Output Control Register Byte 0 Pin # Name Bit 7 - CPUCLK2_ITP/SRCCLK7 Enable Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - - - - SRCCLK6 Enable SRCCLK5 Enable SRCCLK4 Enable SRCCLK3 Enable SRCCLK2 Enable SRCCLK1 Enable SRCCLK0 Enable Control Function Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable SMBus Table: Spreading and Device Behavior Control Register Byte 1 Pin # Name Control Function Bit 7 PCI_F0 Enable Output Enable Bit 6 DOT_96MHz Enable Output Enable Bit 5 USB_48MHz Enable Output Enable Bit 4 REFOUT Enable Output Enable Bit 3 RESERVED Bit 2 CPUCLK1 Output Enable Bit 1 CPUCLK0 Output Enable Bit 0 Spread Spectrum Mode Spread Off SMBus Table: Output Control Register Byte 2 Pin # Name Bit 7 PCICLK5 Bit 6 PCICLK4 Bit 5 Bit 4 PCICLK3 PCICLK2 Bit 3 Bit 2 Bit 1 Bit 0 PCI_F1 Enable Control Function Output Enable Output Enable Output Enable Output Enable RESERVED RESERVED RESERVED Output Enable Type RW RW RW RW RW RW RW RW 0 DISABLE DISABLE DISABLE DISABLE DISABLE DISABLE DISABLE DISABLE 1 ENABLE ENABLE ENABLE ENABLE ENABLE ENABLE ENABLE ENABLE Type RW RW RW RW 0 Disable Disable Disable Disable 1 Enable Enable Enable Enable RW Disable RW Disable RW SPREAD OFF Enable Enable SPREAD ON Type RW RW RW RW 0 Disable Disable Disable Disable 1 Enable Enable Enable Enable RW Disable Enable PWD 1 1 1 1 1 1 1 1 PWD 1 1 1 1 1 1 1 0 PWD 1 1 1 1 1 1 1 1 0819G—12/06/04 DataSheet4 U .com 11 11 Page

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