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PDF ICS954119 Data sheet ( Hoja de datos )
| Número de pieza | ICS954119 | |
| Descripción | Programmable Timing Control Hub | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS954119
Advance Information
Programmable Timing Control Hub™ for Next Gen P4™ processor
Recommended Application:
CK410 compliant clock
Output Features:
• 2 - 0.7V current-mode differential CPU pairs
• 1 - 0.7V current-mode differential SRC pair
• 6 - PCI (33MHz)
• 3 - PCICLK_F, (33MHz) free-running
• 1 - USB, 48MHz
• 1 - 24/48 MHz
• 1 - DOT, 96MHz, 0.7V current differential pair
• 2 - REF, 14.318MHz
• 5 - PCI-Express 0.7V current differential pairs
Key Specifications:
• CPU/SRC outputs cycle-cycle jitter < 85ps
• PCI outputs cycle-cycle jitter < 250ps
• +/- 300ppm frequency accuracy on CPU & SRC clocks
Features/Benefits:
• Programmable output frequencies
• Programmable output skew.
• Programmable spread percentage for EMI control.
• Programmable watch dog safe frequency.
• Supports tight ppm accuracy clocks for Serial-ATA
• Supports spread spectrum modulation, 0 to -0.5%
down spread, ±0.25% center spread, and ±0.3%
center spread
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
• Supports undriven differential CPU, SRC pair in PD#
for power management.
Functionality
Bit4 Bit3 Bit2 Bit1 Bit0 CPU PCIEX SRC
FSLC FSLB FSLA MHz MHz MHz
0 0 0 0 0 266.66 100.00 100.00
0 0 0 0 1 133.33 100.00 100.00
0 0 0 1 0 200.00 100.00 100.00
0 0 0 1 1 166.66 100.00 100.00
0 0 1 0 0 333.33 100.00 100.00
0 0 1 0 1 100.00 100.00 100.00
0 0 1 1 0 400.00 100.00 100.00
0 0 1 1 1 200.00 100.00 100.00
0 1 0 0 0 266.66 133.33 133.33
0 1 0 0 1 133.33 133.33 133.33
0 1 0 1 0 200.00 133.33 133.33
0 1 0 1 1 166.66 125.00 125.00
0 1 1 0 0 333.33 125.00 125.00
0 1 1 0 1 100.00 133.33 133.33
0 1 1 1 0 400.00 133.33 133.33
0 1 1 1 1 200.00 133.33 133.33
1 0 0 0 0 269.33 101.00 101.00
1 0 0 0 1 134.66 101.00 101.00
1 0 0 1 0 202.00 101.00 101.00
1 0 0 1 1 168.33 101.00 101.00
1 0 1 0 0 274.66 103.00 103.00
1 0 1 0 1 137.33 103.00 103.00
1 0 1 1 0 206.00 103.00 103.00
1 0 1 1 1 171.66 103.00 103.00
1 1 0 0 0 279.99 105.00 105.00
1 1 0 0 1 140.00 105.00 105.00
1 1 0 1 0 210.00 105.00 105.00
1 1 0 1 1 174.99 105.00 105.00
1 1 1 0 0 287.99 108.00 108.00
1 1 1 0 1 144.00 108.00 108.00
1 1 1 1 0 216.00 108.00 108.00
1 1 1 1 1 179.99 108.00 108.00
* Entries 00111 & 01111 are 250MHz on the B & C revision.
0875—05/24/04
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.67
33.67
33.67
33.67
34.33
34.33
34.33
34.33
35.00
35.00
35.00
35.00
36.00
36.00
36.00
36.00
Pin Configuration
GND 1
56 VDDPCI
PCICLK3 2
55 PCICLK2
PCICLK4 3
54 PCICLK1
PCICLK5 4
53 PCICLK0
GND 5
VDDPCI 6
PCICLK_F0 7
52 Reset#
51 REF0/FSLC
50 REF1
FSLA/PCICLK_F1 8
FSLB/PCICLK_F2 9
VDD48 10
49 GND
48 X1
47 X2
**SEL24_48#/24_48MHz 11
46 VDDREF
USB_48MHz 12
45 SCLK
GND 13
44 SDATA
DOTT_ 96MHz 14
43 CPUCLKT0
DOTC_96MHz 15
42 CPUCLKC0
Vtt_PwrGd#/PD 16
41 VDDCPU
PCIEXT0 17
40 CPUCLKT1
PCIEXC0 18
39 CPUCLKC1
VDDPCIEX 19
38 GND
GND 20
37 IREF
PCIEXT1 21
36 GNDA
PCIEXC1 22
35 VDDA
PCIEXT2 23
34 VDDPCIEX
PCIEXC2 24
33 PCIEXT4
GND 25
32 PCIEXC4
SRCCLKT 26
31 PCIEXT3
SRCCLKC 27
30 PCIEXC3
VDDSRC 28
29 GND
56-Pin SSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
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Integrated
Circuit
Systems, Inc.
ICS954119
Advance Information
General I2C serial interface information for the ICS954119
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
T starT bit
Slave Address D2(H)
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
Byte N + X - 1
P stoP bit
ACK
Index Block Read Operation
Controller (Host)
ICS (Slave/Receiver)
T starT bit
Slave Address D2(H)
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address D3(H)
RD ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
N Not acknowledge
P stoP bit
Byte N + X - 1
0875—05/24/04
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I2C Table: Programmable Output Divider Register
Byte 20
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
PCIDiv3
PCIDiv2
PCIDiv1
PCIDiv0
Reserved
Reserved
Reserved
Reserved
ICS954119
Advance Information
Control Function
PCI Divider Ratio
Programming Bits
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0000:/2
0001:/3
0010:/5
0011:/15
0
0100:/4
0101:/6
0110:/10
0111:/30
-
-
-
-
1
1000:/8
1001:/12
1010:/20
1011:/60
-
-
-
-
1100:/16
1101:/24
1110:/40
1111:/120
PWD
X
X
X
X
X
X
X
X
0875—05/24/04
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| PDF Descargar | [ Datasheet ICS954119.PDF ] | |
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