PDF ICS954101 Data sheet ( Hoja de datos )

Número de pieza	ICS954101
Descripción	Programmable Timing Control Hub for Desktop P4 Systems
Fabricantes	Integrated Circuit Systems
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No Preview Available ! www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS954101 Programmable Timing Control Hub™ for Desktop P4™ Systems Recommended Application: CK410 clock, Intel Yellow Cover part Output Features: • 2 - 0.7V current-mode differential CPU pairs • 6 - 0.7V current-mode differential SRC pair for SATA and PCI-E • 1 - 0.7V current-mode differential CPU/SRC selectable pair • 6 - PCI (33MHz) • 3 - PCICLK_F, (33MHz) free-running • 1 - USB, 48MHz • 1 - DOT, 96MHz, 0.7V current differential pair • 1 - REF, 14.318MHz Features/Benefits: • Supports tight ppm accuracy clocks for Serial-ATA and PCI-Express • Supports spread spectrum modulation, 0 to -0.5% down spread • Supports CPU clks up to 400MHz • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning • Supports undriven differential CPU, SRC pair in PD# for power management. Key Specifications: • CPU outputs cycle-cycle jitter < 85ps • SRC output cycle-cycle jitter <125ps • PCI outputs cycle-cycle jitter < 500ps • +/- 300ppm frequency accuracy on CPU & SRC clocks Functionality FS_C1 FS_B2 FS_A2 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 CPU SRC MHz MHz 266.66 100.00 133.33 100.00 200.00 100.00 166.66 100.00 333.33 100.00 100.00 100.00 400.00 100.00 RESERVED PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 REF MHz 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 USB MHz 48.00 48.00 48.00 48.00 48.00 48.00 48.00 48.00 DOT MHz 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 1. FS_C is a three-level input. Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FS_B and FS_A are low-threshold inputs. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Pin Configuration VDDPCI 1 GND 2 PCICLK3 3 PCICLK4 4 PCICLK5 5 GND 6 VDDPCI 7 ITP_EN/PCICLK_F0 8 PCICLK_F1 9 PCICLK_F2 10 VDD48 11 USB_48MHz 12 GND 13 DOTT_96MHz 14 DOTC_96MHz 15 FS_B/TEST_MODE 16 Vtt_PwrGd#/PD 17 FS_A_410 18 SRCCLKT1 19 SRCCLKC1 20 VDDSRC 21 SRCCLKT2 22 SRCCLKC2 23 SRCCLKT3 24 SRCCLKC3 25 SRCCLKT4_SATA 26 SRCCLKC4_SATA 27 VDDSRC 28 56 PCICLK2 55 PCICLK1 54 PCICLK0 53 FS_C/TEST_SEL 52 REFOUT 51 GND 50 X1 49 X2 48 VDDREF 47 SDATA 46 SCLK 45 GND 44 CPUCLKT0 43 CPUCLKC0 42 VDDCPU 41 CPUCLKT1 40 CPUCLKC1 39 IREF 38 GNDA 37 VDDA 36 CPUCLKT2_ITP/SRCCLKT_7 35 CPUCLKC2_ITP/SRCCLKC_7 34 VDDSRC 33 SRCCLKT6 32 SRCCLKC6 31 SRCCLKT5 30 SRCCLKC5 29 GND 56-pin SSOP & TSSOP 0815D—06/21/04 DataSheet4 U .com 1 page www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS954101 General I2C serial interface information for the ICS954101 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 (H) • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • Controller (host) sends the data byte count = X • ICS clock will acknowledge • Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit How to Read: • Controller (host) will send start bit. • Controller (host) sends the write address D2 (H) • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • Controller (host) will send a separate start bit. • Controller (host) sends the read address D3 (H) • ICS clock will acknowledge • ICS clock will send the data byte count = X • ICS clock sends Byte N + X -1 • ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). • Controller (host) will need to acknowledge each byte • Controllor (host) will send a not acknowledge bit • Controller (host) will send a stop bit Index Block Write Operation Controller (Host) ICS (Slave/Receiver) T starT bit Slave Address D2(H) WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK Byte N + X - 1 P stoP bit ACK Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T starT bit Slave Address D2(H) WR WRite ACK Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK ACK ACK Data Byte Count = X Beginning Byte N N Not acknowledge P stoP bit Byte N + X - 1 0815D—06/21/04 DataSheet4 U .com 5 5 Page www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS954101 Electrical Characteristics - REF-14.318MHz TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX Long Accuracy ppm see Tperiod min-max values -300 Clock period Tperiod 14.318MHz output nominal 69.82700 Absolute Min/Max Clock period Tabs Nominal 68.82033 Output High Voltage VOH IOH = -1 mA 2.4 Output Low Voltage VOL IOL = 1 mA Output High Current IOH V OH @MIN = 1.0 V, OH@MAX = 3.135 V V -29 Output Low Current IOL VOL @MIN = 1.95 V, @MAX = 0.4 V VOL 29 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 1 Skew tsk1 VT = 1.5 V Duty Cycle dt1 VT = 1.5 V 45 Jitter tjcyc-cyc VT = 1.5 V 1Guaranteed by design, not 100% tested in production. 300 69.85500 70.86224 0.4 -23 27 2 2 500 55 1000 UNITS ppm ns ns V V mA mA ns ns ps % ps NOTES 1 1 2 1 1 1 1 1 1 1 1 1 0815D—06/21/04 DataSheet4 U .com 11 11 Page

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