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SPI Voltage Output denseDAC - Analog Devices

Número de pieza AD5668
Descripción SPI Voltage Output denseDAC
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo
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AD5668 datasheet

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AD5668 pdf
Data Sheet
AD5628/AD5648/AD5668
VDD = 2.7 V to 3.6 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
A Grade1
B Grade1
Min Typ Max Min Typ Max Unit
Conditions/Comments
STATIC PERFORMANCE2
AD5628
Resolution
12
12
Bits
Relative Accuracy
±0.5 ±4
±0.5 ±1 LSB
Differential Nonlinearity
±0.25
±0.25 LSB
AD5648
Resolution
14
14
Bits
See Figure 9
Guaranteed monotonic by design
(see Figure 12)
Relative Accuracy
±2 ±8
±2 ±4 LSB
See Figure 8
Differential Nonlinearity
±0.5
±0.5 LSB
Guaranteed monotonic by design
(see Figure 11)
AD5668
Resolution
16
16
Bits
Relative Accuracy
±8 ±32
±8 ±16 LSB
See Figure 7
Differential Nonlinearity
±1
±1 LSB
Guaranteed monotonic by design
(see Figure 10)
Zero-Code Error
6 19
6 19 mV
All 0s loaded to DAC register (see Figure 26)
Zero-Code Error Drift
±2
±2 µV/°C
Full-Scale Error
−0.2 −1
−0.2 −1 % FSR All 1s loaded to DAC register (see Figure 27)
Gain Error
Gain Temperature Coefficient
±1
±2.5
±1
±2.5
% FSR
ppm
Of FSR/°C
Offset Error
DC Power Supply Rejection
Ratio3
DC Crosstalk 3
(External Reference)
DC Crosstalk 3
(Internal Reference)
±6 ±19
–80
10
5
10
25
10
±6 ±19
–80
10
5
10
25
10
mV
dB VDD ± 10%
µV
µV/mA
µV
µV
µV/mA
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
Due to load current change
Due to powering down (per channel)
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
Due to load current change
OUTPUT CHARACTERISTICS3
Output Voltage Range
Capacitive Load Stability
0
DC Output Impedance
Short-Circuit Current
Power-Up Time
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
0
VDD
2
10
0.5
30
4
40 55
VDD
14.6
0
0
VDD
2
10
0.5
30
4
40 55
VDD
14.6
V
nF
nF
mA
µs
µA
kΩ
RL = ∞
RL = 2 kΩ
VDD = 3 V
Coming out of power-down mode, VDD = 3 V
VREF = VDD = 5.5 V (per DAC channel)
REFERENCE OUTPUT
Output Voltage
AD5628/AD5648/AD5668-1
Reference TC3
1.247
5
1.253 1.247
15 5
1.253 V
At ambient
15 ppm/°C TSSOP
Reference Output
Impedance
15 5 15 ppm/°C LFCSP
15 ppm/°C WLCSP
7.5 7.5 kΩ
Rev. I | Page 5 of 29

5 Page

AD5668 arduino
AD5628/AD5648/AD5668
Data Sheet
BALL A1
INDICATOR
1234
GND SCLK DIN SYNC
A
VOUTB LDAC VDD VOUTA
B
VOUTF VOUTD VOUTE VOUTC
C
VOUTH CLR VREF VOUTG
D
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
Figure 6. 16-Lead WLCSP
Table 7. 16-Lead WLCSP Pin Function Descriptions
Pin. No. Mnemonic Description
B2 LDAC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows
all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low.
A4 SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges
of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of SYNC acts as an
interrupt and the write sequence is ignored by the device.
B3 VDD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
B4 VOUTA
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
B1 VOUTB
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
C4 VOUTC
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
C2 VOUTD
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
D3 VREFIN/VREFOUT The AD5628/AD5648/AD5668 have a common pin for reference input and reference output. When using the
internal reference, this is the reference output pin. When using an external reference, this is the reference input
pin. The default for this pin is as a reference input.
D2 CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored.
When CLR is activated, the input register and the DAC register are updated with the data contained in the CLR
code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
C3 VOUTE
Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.
C1 VOUTF
Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.
D4 VOUTG
Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.
D1 VOUTH
Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.
A1 GND
Ground Reference Point for All Circuitry on the Part.
A3 DIN
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
A2 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates of up to 50 MHz.
Rev. I | Page 10 of 29

10 Page





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