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PDF LC7982A Data sheet ( Hoja de datos )
| Número de pieza | LC7982A | |
| Descripción | LCD Dot Matrix Graphics Display Controller | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
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Ordering number : EN5946
CMOS IC
LC7982A
LCD Dot Matrix Graphics Display Controller
Overview
The LC7982A is an LCD dot matrix graphics display
controller IC. It stores display data sent from an 8-bit
microcontroller in external display RAM and generates
dot matrix LCD drive signals. Applications can select
either of two modes: graphics mode, in which each bit in
external RAM controls the on/off state of an individual
pixel (dot) on the LCD, and character mode, in which
character codes are stored in external RAM and the dot
pattern is generated using the built-in character generator
ROM. Thus the LC7982A can support a wide range of
applications. The LC7982A is fabricated in a CMOS
process, and in conjunction with a CMOS microcontroller,
can implement low-power LCD display systems. This
device differs from the LC7981 only in the data stored in
the built-in character generator ROM.
Features
• LCD dot matrix and graphics display controller
• Display control capacity
Graphics mode
512 K dots (216 bytes)
Character mode
4096 characters (212 bytes)
• Character generator ROM 7360 bits
· European character support
Character font: 5 × 7 dots 160 characters 192 characters
Character font: 5 × 11 dots 32 characters total
(Can be expanded by up to 4 KB using external ROM.)
• Supports interfacing with 8-bit microcontrollers.
• Display duty (program selectable)
— From static to 1/256 duty
• Extensive set of command functions
— Scroll, cursor on/off/blink, character blinking, bit
manipulation
• Display methods : Method A and method B (program
selectable)
• Built-in oscillator circuit (Using an external resistor and
capacitor)
• Low power
• +5V single-voltage power supply
Package Dimensions
unit: mm
3055A-QFP60C
[LC7982A]
SANYO: QFP60C (QIP60C)
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
O1698RM (OT) No. 5946-1/18
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• External RAM and ROM interface
MA0 to
MA15
MD0 to
MD7
RD0 to
RD7
LC7982A
Read Cycle at Ta = –20 to +75°C, VDD = 5 V ±5%, GND = 0 V
Parameter
Symbol
Conditions
MA0 to MA15 read address delay time
MD0 to MD7, RD0 to RD7 setup time
tDMAR
tSMDR
Write Cycle at Ta = –20 to +75°C, VDD = 5 V ±5%, GND = 0 V
Parameter
Symbol
Conditions
Memory address setup time
WE pulse width
Memory data setup time
Memory address hold time
Memory data hold time
tSMAW
tWWE
tSMDW
tHMAW
tHMDW
Notes: • With no loads on any of the output pins.
• All measurements are made at 1.5 V.
• Driver IC interface
Ratings
min typ
105
max
95
Unit
ns
ns
min
50
350
250
50
50
Ratings
typ
max
Unit
ns
ns
ns
ns
ns
D1, D2
Ta = –20 to +75°C, VDD = 5 V ±5%, GND = 0 V
Parameter
Symbol
Conditions
Clock cycle time
Clock phase difference
Clock rise and fall times
D1 and D2 phase difference
MA and MB phase difference
FLM phase difference
tCYC
tDCL
tCRF
tDD
tDMA
tDFM
Notes: • With no loads on any of the output pins.
• Measurements other than those with a specified measurement point are made at 0.5 VDD.
DataSheet4 U .com
min
400
Ratings
typ
max
100
30
100
200
200
Unit
ns
ns
ns
ns
ns
ns
No. 5946-5/18
5 Page 
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LC7982A
• Cursor address (high order) setting (RAM read/write high-order address)
Register
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Instruction register
01 00001011
Cursor address counter
(High-order byte)
00
(Cursor address high-order byte) binary
These instructions together write the cursor address value into the cursor address register. The cursor address indicates
the address used for refering to RAM for the display data or character code. That is, the data at the address specified by
the cursor address will be read or written. In character display mode, the cursor is displayed at the position specified by
the cursor address.
While the cursor address is a 16-bit value formed from high-order and low-order bytes, applications must only use
cursor addresses that obey the following restrictions.
When the application rewrites (sets)
1 both the low-order and high-order bytes.
The application must first set the low-order
byte and then set the high-order byte.
When the application only needs to rewrite After writing the low-order byte, the appli-
2 the low-order byte
cation must also write the high-order byte.
The application should simply write the
When the application only needs to rewrite high-order byte.
3 the high-order byte
There is no need for it to write the
low-order byte.
The cursor address counter is a 16-bit increment-only counter with set and reset functions. When the nth bit changes
from 1 to 0, bit n+1 is incremented. When the low-order byte is set, if the set caused the MSB in the low-order byte to
change from 1 to 0, the LSB in the high-order byte will be incremented. Therefore, applications must set both the low-
order and the high-order bytes in that order when setting the cursor address.
• Display data write
Register
Instruction register
RAM
R/W
0
0
RS
1
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00001100
MSB (Pattern data or character code) LSB
When 8 bits of data are written by writing the instruction code 0CH to the instruction register when RS is 0, that data
will be written as either display data or a character code to the RAM address specified by the cursor address counter.
The value of the cursor address counter is incremented by 1 after the write.
• Display data read
Register
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Instruction register
01 00001101
RAM
10
MSB (Pattern data or character code) LSB
Applications can read out data in RAM after the LC7982A has been set to the readout state by writing the instruction
code 0DH to the instruction register when RS is 0. The data readout procedure is described below.
When this instruction is executed, the contents of the data output register will be output from the pins DB0 to DB7.
After that, the RAM data specified by the cursor address will be transferred to the data output register. Additionally,
the cursor address will be incremented by 1. As a result, the correct data will not be read out on the first readout after
the cursor address is set, but the specified data will be read out on the second read. Accordingly, applications that read
data out after setting the cursor address must perform a single dummy read operation.
• Bit clear
Register
Instruction register
Bit clear
• Bit set
R/W
0
0
RS
1
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00001110
0 0 0 0 0 (NB – 1) binary
Register
Instruction register
Bit set
R/W RS
01
00
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00001111
0 0 0 0 0 (NB – 1) binary
The bit clear and bit set instructions set a specified bit in a byte in display data RAM to 0 or 1, respectively. The bit
clear instruction clears the bit specified by NB to 0, and the bit set instruction sets the bit to 1. The RAM address is
determined by the cursor address, and the cursor address is automatically incremented by 1 after the instruction is
executed. NB must be a value in the range 1 to 8. A value of 1 specifies the LSB and a value of 8 specifies the MSB.
No. 5946-11/18
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