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PDF ADM1064 Data sheet ( Hoja de datos )

Número de pieza ADM1064
Descripción Super Sequencer with Voltage Readback ADC
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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Data Sheet
FEATURES
Complete supervisory and sequencing solution for up to
10 supplies
10 supply fault detectors enable supervision of supplies to
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures
5 selectable input attenuators allow supervision of supplies to
14.4 V on VH
6 V on VP1 to VP4 (VPx)
5 dual-function inputs, VX1 to VX5 (VXx)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
10 programmable driver outputs, PDO1 to PDO10 (PDOx)
Open-collector with external pull-up
Push/pull output, driven to VDDCAP or VPx
Open collector with weak pull-up to VDDCAP or VPx
Internally charge-pumped high drive for use with external
N-FET (PDO1 to PDO6 only)
SE implements state machine control of PDO outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
12-bit ADC for readback of all supervised voltages
2 auxiliary (single-ended) ADC inputs
Reference input (REFIN) has 2 input options
Driven directly from 2.048 V (±0.25%) REFOUT pin
More accurate external reference for improved ADC
performance
Device powered by the highest of VPx, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 40-lead LFCSP and 48-lead TQFP packages
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
Super Sequencer with
Voltage Readback ADC
ADM1064
FUNCTIONAL BLOCK DIAGRAM
AUX1 AUX2
REFIN REFOUT REFGND SDA SCL A1 A0
ADM1064
VREF
SMBus
INTERFACE
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
VP4
VH
AGND
12-BIT
SAR ADC
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
SEQUENCING
ENGINE
EEPROM
CONFIGURABLE
OUTPUT
DRIVERS
(HV CAPABLE OF
DRIVING GATES
OF N-FET)
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
VDD
ARBITRATOR
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
PDO10
PDOGND
VDDCA P
VCCP
GND
Figure 1.
GENERAL DESCRIPTION
The ADM1064 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple supply systems. In addition
to these functions, the ADM1064 integrates a 12-bit ADC that
can be used to accurately read back up to 12 separate voltages.
The device also provides up to 10 programmable inputs for moni-
toring undervoltage faults, overvoltage faults, or out-of-window
faults on up to 10 supplies. In addition, 10 programmable outputs
can be used as logic enables. Six of these programmable outputs can
provide up to a 12 V output for driving the gate of an N-FET
that can be placed in the path of a supply.
For more information about the ADM1064 register map, refer
to the AN-698 Application Note.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 page




ADM1064 pdf
ADM1064
The logical core of the device is a sequencing engine (SE). This
state machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs, based
on the condition of the inputs.
Data Sheet
The device is controlled via configuration data that can be
programmed into an EEPROM. The entire configuration can
be programmed using an intuitive GUI-based software package
provided by Analog Devices, Inc.
DETAILED BLOCK DIAGRAM
REFIN REFOUT
AUX2 AUX1
REFGND SDA SCL A1 A0
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
VP4
VH
AGND
VDDCAP
SELECTABLE
ATTENUATOR
SELECTABLE
ATTENUATOR
VDD
ARBITRATOR
ADM1064
VREF
SMBus
INTERFACE
12-BIT
SAR ADC
GPI SIGNAL
CONDITIONING
SFD
GPI SIGNAL
CONDITIONING
SFD
SFD
SFD
REG 5.25V
CHARGE PUMP
DEVICE
CONTROLLER
OSC
EEPROM
CONFIGURABLE
OUTPUT DRIVER
(HV)
SEQUENCING
ENGINE
CONFIGURABLE
OUTPUT DRIVER
(HV)
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
CONFIGURABLE
OUTPUT DRIVER
(LV)
CONFIGURABLE
OUTPUT DRIVER
(LV)
PDO7
PDO8
PDO9
PDO10
PDOGND
GND
VCCP
Figure 2.
Rev. E | Page 4 of 31

5 Page





ADM1064 arduino
ADM1064
Data Sheet
Pin No.
40-Lead 48-Lead
LFCSP TQFP
38 45
39 46
40 47
N/A2
Mnemonic
AUX1
VDDCAP
GND1
EPAD
Description
Auxiliary, Single-Ended ADC Input.
Device Supply Voltage. Linearly regulated from the highest of the VPx, VH pins to a typical of 4.75 V.
Note that the capacitor must be connected between this pin and GND. A 10 μF capacitor is
recommended for this purpose.
Supply Ground.
Exposed Pad. The LFCSP has an exposed pad on the bottom. This pad is a no connect (NC). If possible, this
pad should be soldered to the board for improved mechanical stability.
1 In a typical application, all ground pins are connected together.
2 N/A is not applicable.
Rev. E | Page 10 of 31

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