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PDF IDT723644 Data sheet ( Hoja de datos )

Número de pieza IDT723644
Descripción (IDT7236x4) CMOS SyncBiFIFOTM WITH BUS-MATCHING
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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CMOS SyncBiFIFOTM WITH BUS-MATCHING
256 x 36 x 2,
512 x 36 x 2,
1,024 x 36 x 2
IDT723624
IDT723634
IDT723644
.EATURES:
Memory storage capacity:
IDT723624 – 256 x 36 x 2
IDT723634 – 512 x 36 x 2
IDT723644 – 1,024 x 36 x 2
Clock frequencies up to 83 MHz (8 ns access time)
Two independent clocked FIFOs buffering data in opposite
directions
Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRB flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
Serial or parallel programming of partial flags
Port B bus sizing of 36-bits (long word), 18-bits (word) and
9-bits (byte)
Big- or Little-Endian format for word and byte bus sizes
Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or coinci-
dent (simultaneous reading and writing of data on a single clock
edge is permitted)
Auto power down minimizes power dissipation
Available in space saving 128-pin Thin Quad Flatpack (TQFP)
Industrial temperature range (40°C to +85°C) is available
.UNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
MRS1
PRS1
FFA/IRA
AFA
SPM
FS0/SD
FS1/SEN
A0-A35
EFA/ORA
AEA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
36
36
MBF2
Mail 1
Register
3w6 ww.RD2A5Ma6AtxRaR3AS6Yhee36t4U.com
512 x 36
1,024 x 36
FIFO1
Write
Pointer
Read
Pointer
Status Flag
Logic
Programmable Flag
Offset Registers
Timing
Mode
10
FIFO2
Status Flag
Logic
Read
Pointer
Write
Pointer
RAM ARRAY
36 256 x 36
512 x 36
1,024 x 36
36
Mail 2
Register
IDT, the IDT logo are registered trademark of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
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MBF1
36
EFB/ORB
AEB
36
FIFO2,
Mail2
Reset
Logic
FWFT
B0-B35
FFB/IRB
AFB
MRS2
PRS2
Port-B
Control
Logic
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
3270 drw01
AUGUST 2001
DSC-3270/2

1 page




IDT723644 pdf
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IDT723624/723634/723644 CMOS SyncBiFIFOWITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTIONS (CONTINUED)
Symbol
Name
FS1/SEN FlagOffset
Select 1/
Serial Enable,
I/O
I
FS0/SD FlagOffset
Select 0/
Serial Data
I
MBA Port A Mailbox I
Select
MBB Port B Mailbox I
Select
MBF1
Mail1 Register
Flag
O
MBF2
Mail2 Register
Flag
O
MRS1
FIFO1 Master
Reset
I
MRS2
FIFO2 Master
Reset
I
PRS1
FIFO1 Partial
Reset
I
PRS2
FIFO2 Partial
Reset
I
SIZE(1) Bus Size Select I
SPM(1)
W/RA
W/RB
Serial Program-
ming Mode
Port-A Write/
Read Select
Port-B Write/
Read Select
I
I
I
Description
FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Master Reset,
FS1/SEN and FS0/SD, together with SPM, select the flag offset programming method. Three offset register
programming methods are available: automatically load one of three preset values (8, 16, or 64), parallel load
from Port A, and serial load.
When serial load is selected for flag offset register programming, FS1/SENis used as an enable synchronous to
the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load the bit present on
FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 32 for the
723624, 36 for the 723634, and 40 for the 723644. The first bit write stores the Y1 register MSB and the last bit
write stores the X2 register LSB.
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35
outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level selects
FIFO2 output register data for output.
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35
outputs are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level selects
FIFO1 output register data for output.
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the
mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when
a Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of
FIFO1.
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the
mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a
Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of
FIFO2.
A LOW on this pin iniwtiawlizews .thDeaFItFaOS1 rheeadeatn4dUwr.itceopominters to the first location of memory and sets the Port B
outputregistertoallzeroes.ALOW-to-HIGHtransitionon MRS1 selectstheprogrammingmethod(serialorparallel)
and one of three programmable flag default offsets for FIFO1 and FIFO2. It also configures Port B for bus size and
endianarrangement. FourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKBmustoccur
while MRS1 is LOW.
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A
output register to all zeroes. A LOW-to-HIGH transition on MRS2 toggled simultaneously with MRS1, selects the
programming method (serial or parallel) and one of the programmable flag default offsets for FIFO2. Four LOW-
to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is LOW.
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B
output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, program
ming method (serial or parallel), and programmable flag settings are all retained.
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A
output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, program
ming method (serial or parallel), and programmable flag settings are all retained.
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is
HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement
for Port B. The level of SIZE must be static throughout device operation.
A LOW on this pin selects serial programming of partial flag offsets. A HIGH on this pin selects parallel
programming or default offsets (8, 16, or 64).
A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to- HIGH transition of
CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH transition of
CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW.
NOTE:
1. BM, SIZE and SPM are not TTL compatible. These inputs should be tied to GND or VCC.
5
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IDT723644 arduino
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IDT723624/723634/723644 CMOS SyncBiFIFOWITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
performingaformalreadoperation.RefertoFigure3(MasterReset)foraFirst the offset registers are (A7-A0), (A8-A0), or (A9-A0) for the IDT723624,
Word Fall Through select timing diagram.
IDT723634, or IDT723644, respectively. The highest numbered input is used
FollowingMasterReset,thelevelappliedtotheBE/FWFTinputtochoose asthemostsignificantbitofthebinarynumberineachcase.Validprogramming
the desired timing mode must remain static throughout FIFO operation.
values for the registers range from 1 to 252 for the IDT723624; 1 to 508 for the
IDT723634; and 1 to 1,020 for the IDT723644. After all the offset registers are
PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS programmed from Port A, the Port B Full/Input Ready flag (FFB/IRB) is set
FourregistersintheIDT723624/723634/723644areusedtoholdtheoffset HIGH, and both FIFOs begin normal operation. Refer to Figure 5 for a timing
values for the Almost-Empty and Almost-Full flags. The Port B Almost-Empty diagram illustration of parallel programming of the flag offset values.
flag (AEB) Offset register is labeled X1 and the Port A Almost-Empty flag (AEA)
Offset register is labeled X2. The Port A Almost-Full flag (AFA) Offset register SERIAL LOAD
islabeledY1andthePortBAlmost-Fullflag(AFB)OffsetregisterislabeledY2. ToprogramtheX1,X2,Y1,andY2registersserially,initiateaMasterReset
The index of each register name corresponds to its FIFO number. The offset with SPM LOW, FS0/SD LOW and FS1/SEN HIGH during the LOW-to-HIGH
registers can be loaded with preset values during the reset of a FIFO, transitionof MRS1 and MRS2.Afterthisresetiscomplete,theXandYregister
programmed in parallel using the FIFOs Port A data inputs, or programmed values are loaded bit-wise through the FS0/SD input on each LOW-to-HIGH
in serial using the Serial Data (SD) input (see Table 1).
transition of CLKA that the FS1/SENinput is LOW. There are 32-, 36-, or 40-
SPM, FS0/SD and FS1/SEN function the same way in both IDT Standard bitwritesneededtocompletetheprogrammingfortheIDT723624,IDT723634,
and FWFT modes.
or IDT723644, respectively. The four registers are written in the order Y1, X1,
Y2, and finally, X2. The first-bit write stores the most significant bit of the Y1
PRESET VALUES
registerandthelast-bitwritestorestheleastsignificantbitoftheX2register.Each
ToloadaFIFOsAlmost-EmptyflagandAlmost-FullflagOffsetregisterswith register value can be programmed from 1 to 508 (IDT723624), 1 to 1,020
oneofthethreepresetvalueslistedinTable1,theSerialProgramMode(SPM) (IDT723634), or 1 to 2,044 (IDT723644).
andatleastoneoftheflag-selectinputsmustbeHIGHduringtheLOW-to-HIGH Whentheoptiontoprogramtheoffsetregistersseriallyischosen,thePort
transition of its Master Reset input (MRS1, MRS2). For example, to load the AFull/InputReady(FFA/IRA)flagremainsLOWuntilallregisterbitsarewritten.
preset value of 64 into X1 and Y1, SPM, FS0 and FS1 must be HIGH when FFA/IRA is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit
FlFO1reset(MRS1)returnsHIGH.Flag-offsetregistersassociatedwithFIFO2 is loaded to allow normal FIFO1 operation. The Port B Full/Input Ready (FFB/
are loaded with one of the preset values in the same way with FIFO2 Master IRB)flagalsoremainsLOWthroughouttheserialprogrammingprocess,until
Reset(MRS2),toggledsimultaneouslywithFIFO1MasterReset(MRS1).For allregisterbitsarewritten.FFB/IRBissetHIGHbytheLOW-to-HIGHtransition
relevant preset value loading timing diagram, see Figure 3.
of CLKB after the last bit is loaded to allow normal FIFO2 operation.
PARALLEL LOAD FROM PORT A
www.DataSheeSt4eeUF.igcuorem6 for Serial Programming of the Almost-Full Flag and Almost-
Empty Flag Offset Values (IDT Standard and FWFT Modes).
To program the X1, X2, Y1, and Y2 registers from Port A, perform a Master
Reset on both FlFOs simultaneously with SPM HIGH and FS0 and FS1 LOW FIFO WRITE/READ OPERATION
during the LOW-to-HIGH transition of MRS1 and MRS2. After this reset is ThestateofthePortAdata(A0-A35)linesiscontrolledbyPortAChipSelect
complete, the first four writes to FIFO1 do not store data in the RAM but load (CSA)andPortAWrite/Readselect(W/RA).TheA0-A35linesareintheHigh-
the offset registers in the order Y1, X1, Y2, X2. The Port A data inputs used by
TABLE 1 — .LAG PROGRAMMING
SPM FS1/SEN FS0/SD MRS1 MRS2
H H H X
H H H ↑↑
H H L X
H H L ↑↑
H L H X
H L H ↑↑
H L L ↑↑
L H L ↑↑
L H H ↑↑
L L H ↑↑
L L L ↑↑
NOTES:
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
X1 AND Y1 REGlSTERS(1)
64
64
16
16
8
8
Parallel programming via Port A
Serial programming via SD
Reserved
Reserved
Reserved
11
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X2 AND Y2 REGlSTERS(2)
X
64
X
16
X
8
Parallel programming via Port A
Serial programming via SD
Reserved
Reserved
Reserved

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