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PDF IDT72V8988 Data sheet ( Hoja de datos )
| Número de pieza | IDT72V8988 | |
| Descripción | 3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128 | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
128 x 128
IDT72V8988
FEATURES:
• 128 x 128 channel non-blocking switch
• Automatic signal identification (ST-BUS®, GCI)
• 4 RX inputs—32 channels at 64 Kbit/s per serial line
• 4 TX outputs—32 channels at 64 Kbit/s per serial line
• Three-state serial outputs
• Microprocessor Interface (8-bit data bus)
• Frame Integrity for data applications
• 3.3V Power Supply
• Available in 44-pin Plastic Leaded Chip Carrier (PLCC), and
44-pin Plastic Quad Flatpack (PQFP)
• Operating Temperature Range -40°C to +85°C
• 3.3V I/O with 5V Tolerant Inputs
DESCRIPTION:
The IDT72V8988 is an ST-BUS®/GCI compatible digital switch controlled
by a microprocessor. The IDT72V8988 can handle as many as 128,64 Kbit/s
inputandoutputchannels. Those128channelsaredividedinto4serialinputs
and outputs, each of which consists of 32 channels. The IDT72V8988 provides
per-channel variable or constant throughput delay modes and microprocessor
readandwriteaccesstoindividualchannels. Asanimportantfunctionofadigital
switch is to maintain sequence integrity and minimize throughput delay, the
IDT72V8988 is an ideal solution for most switching needs.
FUNCTIONAL DESCRIPTION
Frame sequence, constant throughput delay, and guaranteed minimum
delay are high priority requirements in today’s integrated data and multimedia
networks. The IDT72V8988 provides these functions on a per-channel basis
usingastandardmicroprocessorcontrolinterface. Eachofthefourseriallines
is designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data.
In Processor Mode, the microprocessor can access the input and output time
slots to control other devices such as ISDN transceivers and trunk interfaces.
Supporting both GCI and ST-BUS® formats, IDT72V8988 has incorporated an
internal circuit to automatically identify the polarity and format of the frame
synchronization.
A functional block diagram of the IDT72V8988 device is shown on page 1.
The serial streams operate continuously at 2.048 Mb/s and are arranged in
125µswideframeseachcontaining32,8-bitchannels. Fourinput(RX0-3)and
FUNCTIONAL BLOCK DIAGRAM
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DataShee
C4i F0i VCC GND
ODE
RX0
Receive
RX1 Serial Data
Data
RX2 Streams Memory
RX3
Timing
Unit
Control Register
Output MUX
Connection
Memory
Transmit
Serial Data
Streams
Microprocessor Interface
TX0
TX1
TX2
TX3
DS CS R/W A0/ DTA D0/
A5 D7
5704 drw01
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IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS is a trademark of Mitel Corp.
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
AUGUST 2003
DSC-5704/5
1 page  
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IDT72V8988 3.3V Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
The information switched to the third time slot after the input has entered the
device (for instance, input channel 0 to output channel 3 or input channel 30 to
output channel 1), will always appear on the output three channels later in the
same incoming frame.
Any switching configuration that provides three or more time slots between
input and output channels, will have a throughput delay equal to the difference
between the output and input channels; i.e., the throughput delay will be less
thanoneframe. Table1showsthepossibledelaysfortheIDT72V8988device
in Variable Delay Mode. An example is shown in Figure 3.
SOFTWARE CONTROL
If the A5, A1, A0 address line inputs are LOW then the IDT72V8988 Internal
Control Register is addressed (see Table 2). If A5 input line is high, then the
remaining address input lines are used to select the 32 possible channels per
input or output stream. As explained in the Control Register description, the
address input lines and the Stream Address bits (STA) of the Control register
give the user the capability of selecting all positions of IDT72V8988 Data and
Connect memories. See Figure 6 for accessing internal memories.
The data in the control register consists of Memory Select and Stream
CONSTANT DELAY MODE
In this mode frame integrity is maintained in all switching configurations by
making use of a multiple Data Memory buffer technique where input channels
written in any of the buffers during frame N will be read out during frame N+2.
In the IDT72V8988, the minimum throughput delay achievable in Constant
Delay mode will be 32 time slots; for example, when input time slot 32 (channel
31)isswitchedtooutputtimeslot1(channel0). Likewise,themaximumdelay
is achieved when the first time slot in a frame (channel 0) is switched to the last
time slot in the frame (channel 31), resulting in 94 time slots of delay (see
Figure 4).
To summarize, any input time slot from input frame N will be always switched
to the destination time slot on output frame N+2. In Constant Delay mode the
device throughput delay is calculated according to the following formula:
Address bits, Split Memory and Processor Enable bits (Table 3). In Split Memory
mode (Bit 7 of the Control register) reads are from the Data Memory and writes
are to the Connection Memory LOW. The Memory Select bits allow the
Connection Memory High or LOW or the Data Memory to be chosen, and the
Stream Address bits define internal memory subsections corresponding to input
or output streams.
The Processor Enable bit (bit 6) places every output channel on every
output stream in Processor Mode; i.e., the contents of the Connection Memory
LOW (CML, Table 5) are output on the output streams once every frame unless
the ODE input pin is LOW. If PE bit is HIGH, then the IDT72V8988 behaves as
if bits 2 (Channel Source)and 0 (Output Enable)of every ConnectionMemory
High (CMH, Table 4) locations were set to HIGH, regardless of the actual value.
If PE is LOW, then bit 2 and 0 of each Connection Memory High location operates
normally. In this case, if bit 2 of the CMH is HIGH, the associated TX output
DELAY=[32+(32-IN)+(OUT-1)]
channel is in Processor Mode. If bit 2 of the CMH is LOW, then the contents of
the CML define the source information (stream and channel) of the time slot that
et4U.com IN =the number of the input time slot (from 1 to 32)
OUT = the number of the output time slot (from 1 to 32).
is to be switched to an output.
If the ODE input pin is LOW, then all the serial outputs are high-impedance. DataShee
If ODE is HIGH, then bit 0 (Output Enable) of the CMH location enables (if HIGH)
MICROPROCESSOR PORT
DataSheeto4rUdi.scaobmles (if LOW) for that particular channel.
The IDT72V8988 microprocessor port is a non-multiplexed bus architec- INITIALIZATION
ture. Theparallelportconsistsofan8-bitparalleldatabus(D0-D7),sixaddress
inputlines(A0-A5)andfourcontrollines(CS,DS,R/WandDTA). Thisparallel
microport allows the access to the Control Registers, Connection Memory Low,
Connection Memory High, and the Data Memory. All locations are read/write
access able except for the Data Memory, which can be read only.
Accesses from the microport to the Connection Memory and the Data
Memory are multiplexed with accesses from the input and output TDM ports.
ThiscancausevariableDataAcknowledgedelays(DTA). IntheIDT72V8988
device,theDTA outputprovidesamaximumacknowledgmentdelayof800ns
for read/write operations in the Connection Memory. However, for operations
in the Data Memory (Processor Mode), the maximum acknowledgment delay
During the microprocessor initialization routine, the microprocessor should
program the desired active paths through the matrices, and put all other channels
intothehighimpedancestate. CareshouldbetakenthatnotwoConnectedTX
outputsdrivethebussimultaneously. WiththeCMHsetup,themicroprocessor
controlling the matrices can bring the ODE signal high to relinquish high
impedance state control to the Connection Memory High bits outputs.
As the connection memory can be in any state after a power up, the ODE
pin should be used to hold the TX streams in high-impedance until the per-
channel output enable control in the connection memory high is appropriately
programmed.
can be 1220ns.
TABLE 1 VARIABLE DELAY MODE
Input Channel Output Channel Throughput Delay
n
m=n, n+1 or n+2
m-n+32 time slot
n
m>n+2
m-n time slot
n m<n 32-(n-m) time slot
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TABLE 2 ADDRESS MAPPING
A5 A4 A3 A2 A1 A0
LOCATION
0 X X X 0 0 Control Register
10 0 0 0 0
Channel 0
10 0 0 0 1
Channel 1
1• • • • •
•
1• • • • •
•
1• • • • •
•
1• • • • •
•
1• • • • •
•
11 1 1 1 1
Channel 31
5
5 Page 
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IDT72V8988 3.3V Time Slot Interchange
Digital Switch 128 x 128
AC ELECTRICAL CHARACTERISTICS (1) GCI TIMING
Symbol
Parameter
Min. Typ.(2) Max.
tC4i Clock Period
244
tCL, tCH
Pulse Width
122
tWFH Frame Width High
244
tF0iS FrameSetup
5 20 190
tF0iH Frame Hold
5 20 190
tDAA Data Delay/Clock Active to Active
40
60
tSTiS Serial Input Setup
10
tSTiH Serial Input Hold
10
tr,tf Clock Rise/Fall Time
10
NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Commercial Temperature Range
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
CL = 150pF
et4U.com
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DataShee
F0i
tr
C4i
tWFH
tF0iS
tF0iH
tf tCL tCH
tC4i
TX
Ch. 31
Bit 7
tDAA
RX
Ch. 31
Bit 7
Ch. 0
tSTiS
Ch. 0
Bit 0
tSTiH
Bit 0
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Figure 8. GCI Timing
11
Ch. 0 Bit 1
Ch. 0
Bit 1
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11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet IDT72V8988.PDF ] | |
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