PDF SAA7818HL Data sheet ( Hoja de datos )

Número de pieza	SAA7818HL
Descripción	DVD and CD playback IC
Fabricantes	NXP Semiconductors
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No Preview Available ! www.DataSheet4U.com SAA7818HL DVD and CD playback IC Rev. 03 — 25 November 2004 Product data sheet 1. General description The SAA7818HL is a device for 6 × DVD and 18 × CD playback applications. This device contains an embedded microcontroller which can operate as a 33 MHz or 67 MHz equivalent 80C51 and interfaces to the channel decoder, block decoder and servo processor. New features enable superior playability in both CD and DVD modes. The block decoder has an embedded DVD video authentication module and supports up to 64 Mbit of external SDRAM memory. The data can be fed out in a number of different conﬁgurations including I2S-bus, ATAPI and UDE. This device also includes the option to bypass the external memory altogether, creating a bufferless ATAPI or UDE data path solution. The channel decoder has selectable differential and single-ended HF inputs, which are compatible with the TZA1036 and TZA1038 devices. There is an option to output the data as raw I2S-bus via some programmable data I/O pins. With increased tap setting for the PLL equalizer compared with the SAA7816 device and enhanced playability of black dots and scratches, overall playability has been greatly improved. There are also beneﬁts due to a new defect detector DthaattaaSlhloewest4hUo.lcdoinmg the HF PLL frequency and slicer settings over a defect. These, together with an additional limit equalizer lead to improved tolerance to continuity errors in DVD playback mode. There are also two extra motor gain settings compared to the SAA7816 device and support for copyright protection strategies in games applications. DataShee The servo processor has been upgraded to include an improved defect detection and handling process, an integrated envelope detection circuit and also DC offset compensation on the diode inputs. 2. Features s Host interface: x Supports ATAPI interface x Conﬁgurable as generic DMA interface; for use with external host interface devices x Automatic determination of block length for mode 2; form 1 and form 2 sectors; block length transferred is programmable x Supports synchronous UDE interface x Supports bufferless mode. s Block decoder: x Supports CD-ROM, CDr, CD-DA, VCD, SVCD, CD-I, photo CD and DVD video formats DataSheet4U.com 1 page xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x CHANNEL DECODER ADC BIT DETECTOR AND DEMODULATOR MOTOR/TACHO INTERFACE CD/DVD ERCO MEMORY PROCESSOR CSS MODULE CONTROL REGISTERS BLOCK DECODER INTERFACE DRIVE INTERFACE MULTIMEDIA INTERFACE ERCO SUBCODE INTERFACE DRAM INTERFACE MEMORY PROCESSOR HOST INTERFACE CPU INTERFACE SERVO ADC ADC PCS ACCELERATOR SERVO ACCELERATOR RAM SERVO PROCESSOR MICROCONTROLLER ADDRESS DECODER 1.5 kbytes AUXILLIARY RAM SFRs CPU 1.5 kbytes ROM 736 bytes RAM PORT REGISTER mdb204 Fig 1. Block diagram. 5 Page www.DataSheet4U.com Philips Semiconductors SAA7818HL DVD and CD playback IC et4U.com 9397 750 14312 DataSheet4PUro.dcuocmt data sheet Table 3: Pin description …continued Symbol Pin Type [1] Drive/ Description threshold VSSD(P10) XDA3 156 P 157 O L digital ground 10 for the pad cells DRAM address output; bit 3 XDA2 158 O L DRAM address output; bit 2 XDA1 159 O L DRAM address output; bit 1 XDA0 160 O L DRAM address output; bit 0 XDA10 161 O L DRAM address output; bit 10 VDDD(P11) VSSD(P11) XDD2 162 P digital supply voltage 11 for the pad cells (3.3 V) 163 P digital ground 11 for the pad cells 164 B M/T DRAM data bus input/output; bit 2 XDD1 165 B M/T DRAM data bus input/output; bit 1 XDD0 166 B M/T DRAM data bus input/output; bit 0 XDD3 167 B M/T DRAM data bus input/output; bit 3 XDD4 168 B M/T DRAM data bus input/output; bit 4 XDD5 169 B M/T DRAM data bus input/output; bit 5 XDD6 170 B M/T DRAM data bus input/output; bit 6 XDD7 171 B M/T DRAM data bus input/output; bit 7 VDDD(C5) VSSD(C5) LDQM 172 P digital supply voltage 5 for the core (1.8 V) 173 PDataSheet4U.com digital ground 5 for the core 174 O M SDRAM data mask output LOW XWR 175 O M DRAM write strobe output XRAS 176 O M DRAM RAS strobe output SDCS 177 O M SDRAM chip select output XCAS 178 O M DRAM CAS strobe output XDA12 179 O M DRAM address output; bit 12 XDA13 180 O M DRAM address output; bit 13 SDCK 181 O L SDRAM clock output UDQM 182 O M SDRAM data mask output HIGH VDDD(P12) VSSD(P12) XDD8 183 P digital supply voltage 12 for the pad cells (3.3 V) 184 P digital ground 12 for the pad cells 185 B M/T DRAM data bus input/output; bit 8 XDD9 186 B M/T DRAM data bus input/output; bit 9 XDD10 187 B M/T DRAM data bus input/output; bit 10 XDD11 188 B M/T DRAM data bus input/output; bit 11 XDD12 189 B M/T DRAM data bus input/output; bit 12 XDD15 190 B M/T DRAM data bus input/output; bit 15 XDD14 191 B M/T DRAM data bus input/output; bit 14 XDD13 192 B M/T DRAM data bus input/output; bit 13 VDDD(C6) VSSD(C6) XDA11 193 P 194 P 195 O M digital supply voltage 6 for the core (1.8 V) digital ground 6 for the core DRAM address output; bit 11 DataShee Rev. 03 — 25 November 2004 © Koninklijke Philips Electronics N.V. 2004. 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