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PDF IDT74LVC823A Data sheet ( Hoja de datos )

Número de pieza IDT74LVC823A
Descripción 3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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IDT74LVC823A
3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP
3.3V CMOS 9-BIT
BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
AND 5 VOLT TOLERANT I/O
INDUSTRIALTEMPERATURERANGE
IDT74LVC823A
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
The LVC823A 9-bit bus-interface flip-flop is built using advanced dual
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
metal CMOS technology. The LVC823A device is designed specifically for
machine model (C = 200pF, R = 0)
driving highly capacitive or relatively low-impedance loads. The device is
• VCC = 3.3V ± 0.3V, Normal Range
particularly suitable for implementing wider buffer registers, I/O ports,
• VCC = 2.7V to 3.6V, Extended Range
bidirectional bus drivers with parity, and working registers.
• CMOS power levels (0.4µ W typ. static)
With the clock-enable (CLKEN) input low, the nine D-type edge-triggered
• Rail-to-rail output swing for increased noise margin
flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN
• All inputs, outputs, and I/O are 5V tolerant
high disables the clock buffer, latching the outputs. This device has
• Supports hot insertion
noninverting data (D) inputs. Taking the clear (CLR) input low causes the
• Available in SSOP, QSOP, and TSSOP packages
nine Q outputs to go low, independently of the clock.
A buffered output-enable (OE) input can be used to place the nine outputs
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
in either a normal logic state (high or low logic levels) or a high-impedance
state. OE does not affect internal operations of the latch. Previously stored
data can be retained or new data can be entered while the outputs are in
the high-impedance state.
The LVC823A has been designed with a ±24mA output driver. This
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
To ensure the high-impedance
state
during
power
up
or
power
downD, ataShee
DataSheettO4hUEe r.sechsooimsutlodrbies
tied to VCC through a pullup resistor; the minimum
determined by the current-sinking capability of the
value of
driver.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environment.
FUNCTIONAL BLOCK DIAGRAM
OE
CLR
CLKEN
1
11
14
CLK 13
1D 2
R
C1
1D
23 1Q
DataSheet4U.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2004 Integrated Device Technology, Inc.
TO EIGHT OTHER CHANNELS
1
JANUARY 2004
DSC-4608/2

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IDT74LVC823A pdf
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IDT74LVC823A
3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP
INDUSTRIALTEMPERATURERANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
VLOAD
6
6
VIH 2.7
2.7
VT 1.5
1.5
VLZ 300
300
VHZ 300
300
CL 50
50
VCC(2)= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
VCC
VLOAD
Open
VIN
Pulse (1, 2)
Generator
VOUT
D.U.T.
500GND
RT
500
CL
Test Circuit for All Outputs
LVC Link
SAME PHASE
INPUT TRANSITION
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPHL
tPHL
Propagation Delay
VIH
VT
0V
VOH
VT
VOL
VIH
VT
0V
LVC Link
CONTROL
INPUT
ENABLE
tPZL
DISABLE
tPLZ
OUTPUT
NORMALLY
LOW
SWITCH
VLOAD
tPZH
OUTPUT SWITCH
NORMALLY GND
HIGH
VLOAD/2
VT
tPHZ
VT
0V
VIH
VT
0V
VLOAD/2
VOL+VLZ
VOL
VOH
VOH-VHZ
0V
et4U.comDEFINITIONS:
LVC Link
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse GeneratDor.ataSheetN4OUTE.c: om
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns.
2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
DataShee
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
VLOAD
GND
Open
INPUT
OUTPUT 1
OUTPUT 2
tPLH1
tPHL1
tSK (x)
tSK (x)
VIH
VT
0V
VOH
VT
VOL
VOH
VT
VOL
tPLH2
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
LVC Link
DataSheN1e.OtT4EFUoSr:.ctSoK(mo) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
tSU tH
tREM
tSU tH
Set-up, Hold, and Release Times
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
LVC Link
LOW-HIGH-LOW
PULSE
tW
HIGH-LOW-HIGH
PULSE
Pulse Width
VT
VT
LVC Link
5

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