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PDF ICS9169C-40 Data sheet ( Hoja de datos )
| Número de pieza | ICS9169C-40 | |
| Descripción | System Clock Chip | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS9169C-40
System Clock Chip
General Description
The ICS9169C-40 is a Clock Synthesizer chip for Pentium or
Cyrix CPU based motherboards using PCI.
Features include eight CPU clocks and six PCI clocks. A
Reference Output is available equal to the crystal frequency.
The device meets the Pentium power-up stabilization, which
requires that CPU and PCI clocks be stable within 2ms after
power-up.
The ICS9169C-40 clock output are designed for low EMI
emissions. Controlled rise and fall times, unique output
driver circuits and innovative circuit layout techniques enable
the ICS9169C-40 to have lower EMI than other clock
devices.
Features
8 selectable CPU clocks up to 75MHz
Six synchronous PCI clocks
One Referance Clock at 14.318MHz
Power-up stabilization time = 2ms on all CPU and PCI
clocks, which meets Intel PentiumPro power-up
Low CPU and PCI clock jitter <500ps
Low skew output
Improved output drivers are designed for low EMI
Test Mode
Optional common or mixed supply mode:
(VDD = VDDL1 =VDDL2 = 3.3V)
(VDD = 3.3V, VDDL1=VDDL2 = 2.5)
(VDD = 3.3V, VDDL1 = 3.3V, VDDL2 = 2.5V)
Space saving and low cost 34-pin SSOP package
The ICS9169C-40 accepts a 14.318MHz reference crystal or
clock as its input and runs from a 3.3V supply.
Block Diagram
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Pin Configuration
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34-Pin SSOP
Functionality
3.3V±10%, 0-70°C
Crystal (X1, X2) = 14.31818 MHz
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FS2 FS1 FS0
CPU
PCI
0
0
0
50MHz
33.3MHz
0
0
1
55MHz
36.67MHz
0
1
0
REF/2
REF/4
0
1
1
75MHz
37.5MHz
1
0
0
50MHz
25MHz
1
0
1
55MHz
27.6MHz
1
1
0
60MHz
30MHz
1 1 1 66.6MHz 33.3MHz
9169C-40RevA072897P
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
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ICS169C-40
Technical Pin Function Descriptions
et4U.com
VDD/AVDD
This is the power supply to the internal logic of the device as
well as the following clock output buffers:
PCI (1:6)
REF
This pin may be operated at any voltage between 3.0 and 5.5
volts. Clocks from the listed buffers that it supplies will
have a voltage swing from ground to this level. For the
actual guaranteed high and lowvoltage levels of these clocks,
please consult the AC parameter table in this data sheet.
GND/AGND
This is the power supply ground return pin for the chip.
FS0, FS1, FS2
These pins control the frequency of the clocks at the CPU,
PCI pins. See the Funtionality table at the beginning of this
data sheet for a list of the specific frequencies, and the
selection codes that are necessary to produce these
frequencies. The device reads these pins at power-up. If a
"1" value is desired for a specific frequency selection bit,a
10K ohm restor must be connected from the apporapriate FS
pin to the VDD supply. If a "0" value is desired, then the 10K
resistor must be connected to ground.
REF
This is a fixed frequency clock that runs at the same frequency
as the input reference clock (typically 14.31818 MHz) is and
typically used to drive Video and ISA BUS requirements.
XIN
This pin serves one of two functions. When the device is VDDL (1:2)
used with a crystal, XIN acts as the input pinfor the reference This is the power supply to the CPU clock drivers. This pin
signal that comes from the discrete crystal. When the device may be operated "at any voltage" between 2.5 and 3.3 volts.
is driven by an external clock signal, XIN is the device Clocks from the buffers that it supplies will have a voltage
input pin for that reference clock. This pin also implements swing form ground to this level. For the actual guaranteed
an internal crystal loading capacitor that is conneDcatetdaStoheet4Uhi.gchomand low voltage levels of these clocks. Please consult
ground. See the data tables for the value of the capacitor.
the AC parameter table in this data sheet.
DataShee
XOUT
This pin is used only when the device uses a Crystal as the
reference frequency source. In this mode ofoperation, XOUT
is an output signal that drives (or excites) the discrete crystal.
This pin also implements aninternal crystal loading capacitor
that is connected to ground. See the data tables for the value
of the capacitor.
CPU (1:8)
These pins are the clock outputs that drive processor and
other CPU related circuitry that require clocks which are in
tight skew tolerance with the CPU clock. The voltage swing
of these clocks is controlled by that which is applied to the
VDDL (1:2) pin of the device. See the Functionality table at
the beginning of this data sheet for a list of the specific
frequencies that this clock operates at and the selection
codes that are necessary to produce these frequencies.
PCI (1:6)
Outputs for PCI bus with a skew ≤ 250pS.A high current rate
of 60mA is available at 3.3V. These outputs are supplied from
VDD.
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