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PDF ICS9169C-232 Data sheet ( Hoja de datos )
| Número de pieza | ICS9169C-232 | |
| Descripción | Frequency Generator for Pentium Based Systems | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS9169C-232
Frequency Generator for Pentium™ Based Systems
General Description
The ICS9169C-232 is a low-cost frequency generator
designed specifically for Pentium and Pentium-Pro based
chip set systems. The integrated buffer minimizes skew
and provides all the clocks required. A 14.318 MHz XTAL
oscillator provides the reference clock to generate standard
Pentium frequencies. The CPU clock makes gradual
frequency transitions without violating the PLL timing of
internal microprocessor clock multipliers. A raised
frequency setting of 68.5 MHz is available for Turbo-mode
of the 66.8 MHz CPU. The ICS9169C-232 contains 8 CPU
clocks, 6 PCI clocks, 1 REF at 48MHz and 1 at 24MHz.
Either synchronous (CPU/2) or asynchronous (32 MHz)
PCI bus operation can be selected by latching data on
BSEL input.
Block Diagram
Features
• Strong output drive.
• Eight selectable CPU clocks operate up to 83.3 MHz
• Frequency selections include Turbo-mode speed of 68.5
MHz
• Maximum CPU jitter of ±200ps
• Six BUS clocks support sync or async bus operation
• 250ps skew window for CPU outputs, 500ps skew window for
BUS outputs
• CPU clocks to BUS clocks skew 1-4 ns (CPU early)
• 48 MHz clock for USB support & 24 MHz clock for FD.
• Logic inputs latched at Power-On for frequency selection
saving pins as Input/Output
• Integrated buffer outputs drive up to 30pF loads
• 3.0V - 3.7V supply range, CPU (1:6) outputs 2.5V
(2.375 - 2.6V) VDD option
• 28-pin SOIC or SSOP package
Pin Configuration
DataShee
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VDD Groups:
VDD1 = X1, X2, REF/BSEL
VDD2 = CPU1-6
VDD3 = CPU7-8 & PLL Core
VDD4 = BUS1-6
VDD5 = 48/24 MHz
DataSheet4U.com
9169C-232RevB031897
Latched Inputs:
L1 = BSEL
L2 = FS0
L3 = FS1
L4 = FS2
28-Pin SOIC or SSOP
Functionality
3.3V±10%, 0-70°C
Crystal (X1, X2) = 14.31818 MHz
ADD RESS
S EL ECT
FS2 FS1 FS0
00
0
00
1
01
0
01
1
10
0
10
1
11
0
11
1
CPU(1:8) BU S (1:6)MHz
(MHz)
48MHz 24MHz REF
BSEL=1 BSEL=0
50 25 32 48 24 REF
60 30 32 48 24 REF
66.8 33.4 32 48 24 REF
75.9 32
32 48 24 REF
55 27.5 32 48 24 REF
75.9 37.5 32 48 24 REF
83.3 41.7 32 48 24 REF
68.5 34.25 32
48 24 REF
Pentium is a trademark of Intel Corporation.
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
1 page  
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ICS169C-232
Technical Pin Function Descriptions
VDD1
This is the power supply to the internal logic of the device
as well as the following clock output buffers:
A. REF clock output buffers
B. BUS clock output buffers
C. Fixed clock output buffers
This pin may be operated at any voltage between 3.0 and
5.5 volts. Clocks from the listed buffers that it supplies
will have a voltage swing from ground to this level. For the
actual guaranteed high and low voltage levels of these
clocks, please consult the AC parameter table in this data
sheet.
GND
This is the power supply ground return pin for the internal
logic of the device as well as the following clock output
buffers:
BUS (1:6)
This pin is the clock output that is intended to drive the
systems plug-in card bus. The voltage swing of these
clocks is controlled by the supply that is applied to the
VDD pin of the device. See the Functionality table at the
beginning of this data sheet for a list of the specific
frequencies that this clock operates at and the selection
codes that are necessary to produce these frequencies.
FS0, FS1, FS2
These pins control the frequency of the clocks at the CPU,
CPUL, BUS, SDRAM, AGP and IOAPIC pins. See the Fun-
tionality table at the beginning of this data sheet for a list
of the specific frequencies that this clock operates at and
the selection codes that are necessary to produce these
frequencies. The device reads these pins at power-up and
stores the programmed selection code in an internal data
latch. (See programming section of this data sheet for
configuration circuitry recommendations.
et4U.com
A. REF clock output buffers
BSEL
B. BUS clock output buffers
When this pin is a logic 1, it will place the CPU clocks in
C. CPU clock output buffers
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X1 mode for the CPU clocks and will operate at the
This pin serves one of two functions. When the device is preprogrammed fixed frequency rate. It is a shared pin
used with a crystal, X1 acts as the input pin for the and is programed the same way as the Frequency Select
reference signal that comes from the discrete crystal. pins.
When the device is driven by an external clock signal, X1
is the device’ input pin for that reference clock. This pin VDD 2, 3
also implements an internal crystal loading capacitor that These are the power supply pins for the CPU clock buffers.
is connected to ground. See the data tables for the value of By separating the clock power pins, each group can receive
the capacitor.
the appropriate power decoupling and bypassing necessary
to minimize EMI and crosstalk between the individual signals.
X2 VDD2 can be reduced to 2.5V VDD for advanced processor
This pin is used only when the device uses a Crystal as the clocks, which will bring CPU (1:6) outputs at 0 to 2.5V output
reference frequency source. In this mode of operation, X2 swings.
is an output signal that drives (or excites) the discrete
crystal. This pin also implements an internal crystal loading 48 MHz
capacitor that is connected to ground. See the data tables This is a fixed frequency clock that is typically used to
for the value of the capacitor.
drive Super I/O peripheral device needs.
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CPU (1:8)
This pin is the clock output that drives processor and other
CPU related circuitry that require clocks which are in tight
skew tolerance with the CPU clock. The voltage swing of
these clocks is controlled by that which is applied to the
VDD pin of the device. See the Functionality table at the
beginning of this data sheet for a list of the specific
frequencies this clock operates at and the selection codes
that are necessary to produce these frequencies.
24 MHz
This is a fixed frequency clock that is typically used to
drive Keyboard controller clock needs.
VDD4
This power pin supplies the BUS clock buffers.
REF
This is a fixed frequency clock that runs at the same
frequency as the input reference clock (typically 14.31818
MHz) is and typically used to drive Video and ISA BUS
requirements.
DataSheet4U.com
VDD5
This power pin supplies the 48/24 MHz clocks.
5
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