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PDF M36P0R9070E0 Data sheet ( Hoja de datos )
| Número de pieza | M36P0R9070E0 | |
| Descripción | Multi-Chip Package | |
| Fabricantes | ST Microelectronics | |
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M36P0R9070E0
512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash Memory
128 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
PRELIMINARY DATA
Features summary
■ Multi-chip package
– 1die of 512 Mbit (32Mb x 16, Multiple Bank,
Multi-Level, Burst) Flash Memory
– 1 die of 128Mbit (8Mb x16) PSRAM
FBGA
■ Supply voltage
– VDDF = VCCP = VDDQ = 1.7 to 1.95V
– VPPF = 9V for fast program (12V tolerant)
■ Electronic signature
– Manufacturer Code: 20h
– Device Code: 8819
■ Package
– ECOPACK®
TFBGA107 (ZAC)
■ Security
– 2112-bit user programmable OTP Cells
– 64-bit unique device number
■ 100,000 program/erase cycles per block
Flash memory
■ Synchronous / asynchronous read
– Synchronous Burst Read mode:
108MHz, 66MHz
– Asynchronous Page Read mode
– Random Access: 93ns
■ Programming time
■ Block locking
– All Blocks locked at power-up
DataSheet4U.c–omAny combination of Blocks can be locked
with zero latency
– WPF for Block Lock-Down
– Absolute Write Protection with VPPF = VSS
■ Common Flash Interface (CFI)
– 4µs typical Word program time using Buffer
Enhanced Factory Program command
PSRAM
■ Access time: 70ns
■ Memory organization
– Multiple Bank Memory Array: 64 Mbit
Banks
– Four Extended Flash Array (EFA) Blocks of
64 Kbits
■ Dual operations
– program/erase in one Bank while read in
others
■ Asynchronous Page Read
– Page Size: 4, 8 or 16 Words
– Subsequent read within page: 20ns
■ Low power features
– Partial Array Self Refresh (PASR)
– Deep Power-Down mode (DPD)
■ Synchronous Burst Read/Write
– No delay between read and write
operations
DataShee
November 2005
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
DataSheet4U.com
Rev. 1
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M36P0R9070E0
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TFBGA107 8x11mm - 9x12 active ball array, 0.8mm pitch, package outline . . . . . . . . . . . 22
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M36P0R9070E0
2 Signal descriptions
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to
VRPH (refer to Table 8., Flash Memory DC Characteristics - Voltages).
2.11
PSRAM Chip Enable input (EP)
The Chip Enable input activates the PSRAM when driven Low (asserted). When deasserted
(VIH), the device is disabled, and goes automatically in low-power Standby mode or Deep
Power-down mode.
2.12
PSRAM Write Enable (WP)
Write Enable, WP, controls the Bus Write operation of the PSRAM. When asserted (VIL), the
device is in Write mode and Write operations can be performed either to the configuration
registers or to the memory array.
2.13
PSRAM Output Enable (GP)
Output Enable, GP, provides a high speed tri-state control, allowing fast read/write cycles to be
achieved with the common I/O data bus.
et4U.com
2.14
PSRAM Upper Byte Enable (UBP)
The Upper Byte En-able, UBP, gatDeasttahSehdeaetta4Uon.cothme Upper Byte Data Inputs/Outputs (DQ8-
DQ15) to or from the upper part of the selected address during a Write or Read operation.
DataShee
2.15
PSRAM Lower Byte Enable (LBP)
The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-
DQ7) to or from the lower part of the selected address during a Write or Read operation.
If both LBP and UBP are disabled (High) during an operation, the device will disable the data
bus from receiving or transmitting data. Although the device will seem to be deselected, it
remains in an active mode as long as EP remains Low.
2.16
PSRAM Configuration Register Enable (CRP)
When this signal is driven High, VIH, Write operations load either the value of the Refresh
Configuration Register (RCR) or the Bus configuration register (BCR).
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