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PDF M36P0R9060E0 Data sheet ( Hoja de datos )
| Número de pieza | M36P0R9060E0 | |
| Descripción | Multi-Chip Package | |
| Fabricantes | ST Microelectronics | |
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M36P0R9060E0
512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory
64 Mbit (Burst) PSRAM, 1.8V supply, Multi-Chip Package
Feature summary
■ Multi-Chip Package
– 1 die of 512 Mbit (32Mb x 16, Multiple
Bank, Multi-Level, Burst) Flash memory
– 1 die of 64 Mbit (4Mb x16) PSRAM
FBGA
■ Supply voltage
– VDDF = VCCP = VDDQ = 1.7 to 1.95V
TFBGA107 (ZAC)
– VPPF = 9V for fast program
■ Electronic signature
■ Block locking
– Manufacturer Code: 20h
– All Blocks locked at power-up
– Device Code: 8819
■ ECOPACK® package
Flash memory
■ Synchronous / asynchronous read
– Synchronous Burst Read mode:
108MHz, 66MHz
– Asynchronous Page Read mode
– Random Access: 96ns
■ Programming time
– Any combination of Blocks can be locked
with zero latency
– WPF for Block Lock-Down
– Absolute Write Protection with VPPF = VSS
PSRAM
DataSheet4■U.cUosmer-selectable operating modes
– Asynchronous modes: Random Read, and
Write, Page Read
– Synchronous modes: NOR-Flash, Full
Synchronous (Burst Read and Write)
– 4.2µs typical Word program time using
Buffer Enhanced Factory Program
command
■ Asynchronous Random Read
– Access time: 70ns
■ Memory organization
– Multiple Bank memory array: 64 Mbit banks
– Four Extended Flash Array (EFA) Blocks of
■ Asynchronous Page Read
– Page size: 4, 8 or 16 Words
– Subsequent Read within Page: 20ns
64 Kbits
■ Burst Read
■ Dual operations
– program/erase in one Bank while read in
others
– Fixed length (4, 8, 16 or 32 Words) or
Continuous
■ Low power consumption
– No delay between read and write
– Active current: < 25mA
operations
– Standby current: 140µA
■ Security
– Deep Power-Down current: < 10µA
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
■ 100,000 Program/erase cycles per block
■ Common Flash Interface (CFI)
■ Low-power features
– Partial Array Self-Refresh (PASR)
– Deep Power-Down (DPD) Mode
– Automatic Temperature-compensated Self-
Refresh
DataShee
July 2006
DataSheet4U.com
Rev. 2
1/23
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1
1 page  
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M36P0R9060E0
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TFBGA 107 8x11mm - 9x12 active ball array, 0.8mm pitch, package outline . . . . . . . . . . 19
et4U.com
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M36P0R9060E0
2 Signal descriptions
2.11
PSRAM Chip Enable input (EP)
The Chip Enable input activates the PSRAM when driven Low (asserted). When deasserted
(VIH), the device is disabled, and goes automatically in low-power Standby mode or Deep
Power-down mode, according to the RCR (Refresh Configuration Register) setting.
2.12
PSRAM Write Enable (WP)
Write Enable, WP, controls the Bus Write operation of the PSRAM. When asserted (VIL), the
device is in Write mode and Write operations can be performed either to the configuration
registers or to the memory array.
2.13
PSRAM Output Enable (GP)
When held Low, VIL, the Output Enable, GP, enables the Bus Read operations of the
PSRAM.
2.14
PSRAM Upper Byte Enable (UBP)
The Upper Byte En-able, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-
DQ15) to or from the upper part of the selected address during a Write or Read operation.
et4U.com
2.15
2.16
PSRAM Lower Byte Enable (LBP)
The Lower Byte Enable, LBP, gDaatetasSthheeedta4tUa.coonmthe Lower Byte Data Inputs/Outputs (DQ0-
DQ7) to or from the lower part of the selected address during a Write or Read operation.
If both LBP and UBP are disabled (High), the device will disable the data bus from receiving
or transmitting data. Although the device will seem to be deselected, it remains in an active
mode as long as EP remains Low.
PSRAM Configuration Register Enable (CRP)
When this signal is driven High, VIH, bus read or write operations access either the value of
the Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR)
according to the value of A19.
DataShee
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