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PDF T71L6816A Data sheet ( Hoja de datos )
| Número de pieza | T71L6816A | |
| Descripción | Sixteen-port 10/100 Switch | |
| Fabricantes | Taiwan Memory Technology | |
| Logotipo |  |
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Preliminary T71L6816A
Sixteen-port 10/100 Switch
________________________________________________________
The T71L6816A is a sixteen-port 10/100Mbps dual speed ethernet switch integrated with
a built-in 2K entries of address table and supports a 4Mb external SSRAM. T71L6816A is
also a high performance Fast-Ethernet switch with fully compliance with the IEEE802.3,
802.3u and 802.3x specifications. The T71L6816A can be implemented with external PHY chips
and 4Mb pipe-line SSRAM. By default, it is targeted for applications to the stand -alone
switch for low-cost SOHO and small enterprise market.
Features
l Support sixteen 10/100 Ethernet ports with RMII interface.
l External memory needed for 4Mb pipe-line SSRAM.
l Incorporating with private output buffering scheme to prevent HOL (head of line) blocking.
l Each port support priority-based queues with 4 levels and 802.1p QoS.
l Wire-speed store-and-forward switching with low latency.
l Automatic address learning with filtering of local frames or illegal frames.
l Embedded 2K entries of address look-up table.
l Support full/half duplex operations. DataSheet4U.com
l Support auto-negotiation via MDIO to detect speed and duplex status.
l Serial EEPROM interface for auto-configuration for features.
l Support IEEE802.3x flow control for full-duplex operation.
l Support Back-Pressure flow control for half-duplex operation.
l Support port-trunking mode to aggregate the bandwidth to provide the functions of load-sharing and
link backup.
l Support broadcast storm control scheme.
l Maximum 3 port-based VLAN groups can be defined by user.
l Support port-based port monitoring/snooping defined by user.
l Only one 50Mhz oscillator needed.
l 208-pin BGA, 3.3V with .18 µm CMOS technology.
DataShee
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Change to products or specifications without notice.
P. 1
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Publication Date:Jun. 2001
Revision:0.A
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3. Functional Description
Preliminary T71L6816A
3.1 Reset
The T71L6816A will determine some function features chosen by the content of 24LC02
serial EEPROM which was loaded after power on reset. Also, the T71L6816A will write
the abilities derived from 24LC02 or internal default value if 24LC02 is not present
to connected PHY management registers via MDC/MDIO.
et4U.com
3.2 RMII Interface
The T71L6816A provides the low pin count RMII (Reduced Media Independent Interface)
interface capable of supporting 10/100 Mbps data rates between PHY and T71L6816A.
A single clock, 50MHz, sourced from an external clock input is needed for receive(RX)
and transmit(TX) to provide an independent 2-bit wide (di-bit) transmit and receive
data paths. In the case of the REFCLK is 10 times the data rate, namely, 100Mbps mode,
each data di -bit must be output on TXD[1:0] and input on RXD[1:0] for ten successive
REFCLK cycles.
RMII specification signals are listed below:
Signal Name
REFCLK
CRSDV
RXD[1:0]
TXEN
TXD[1:0]
Direction
(with respect to
PHY)
Input
Output
Output
Input
Input
DaDtiarSehceteit4oUn .com
(with respect to
Use
T71L6816A)
Input
Synchronous clock reference for Rx,
Tx and control interface
Input
Carrier sense / receive data valid
Input
Receive data
Output
Transmit enable
Output
Transmit data
3.3 Data Reception
The port will enter the receive-state when the CRSDV signal in the RMII interface is
asserted and t hen the RMII presents the received data in two-bit(di-bit) format that are
synchronous to the RMII reference clock, namely, REFCLK. The T71L6816A will then try
to identify the occurrence of the SFD(Start Frame Delimiter) pattern “10101011”. Once
the SFD was identified, all preamble data prior to SFD will be discarded and the frame
data will be forwarded and stored in the buffer of the switch.
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Preliminary T71L6816A
For example, if we write VLAN_1[15:8] as “0xff”, VLAN_1[7:0] as “0x00”, VLAN_2[15:8] as
“0x0f” and VLAN_2[7:0] as “0xf0”, the T71L6816A will recognize that VLAN group 1 contains
port 15 to port 8, VLAN group 2 contains port 11 to port 4 and VLAN group 3 contains
port 3 to port 0.
3.14 Port-based Trunking
Trunking scheme allows more than two ports to be connected in parallel between two switchs
to increase the traffic bandwidth. The T71L6816A supports up to four ports to form the
trunking backbone with four different mode to balance traffic load and maximum 400Mbps
of data rate is allowed. Also, the T71L6816A supports the link-redirect scheme for trunking
so that the T71L6816A can backup the link circuit automatically while one link
is down and restore the circuit after the circuit is up.
et4U.com
3.15 Port Monitoring
The T71L6816A provides the simple network monitoring scheme for persons who need to snoop
the traffic input from one specific port. By set “SnoopEn” bit in EEPROM, beyond of the
normal forwarding, the T71L6816A wilDlatmaaSkheeeat4Udu.cpolmication of any packet input from the
specified port defined in SPID and forward this copy to another specific port defined
in MPID, i.e., only one pair of snooping/monitoring port can be defined.
DataShee
3.16 Queue Priority
There are four queues supported by T71L6816A with different priorities for every output
port. In general, the T71L6816A will treat all output packets as the same and put them
into one queue with lowest priority. However, if any packet which contains the 802.1Q
tagging with 3-bit priority value larger than 0 or comes from one port defi ned as high
priority is found, those packets will be put into other three output queues with more
higher priorities. The T71L6816A will use weighted round-robin method to serve every
output queue for each port that has packets in queues.
3.17 Interface of PHY management
The T71L6816A supports the PHY management through two signal lines, MDC and MDIO. The
T71L6816A will write physical abilities to the register 4 and register 5 of connected
PHYs and restart the auto -negotiation process by polling each PHYs with PHY address
DataSheet4U.coTmaiwan Memory Technology, Copy-Right reserved.
Change to products or specifications without notice.
P. 11
Publication Date:Jun. 2001
Revision:0.A
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