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PDF DP83956A Data sheet ( Hoja de datos )
| Número de pieza | DP83956A | |
| Descripción | (DP83955A / DP83956A) LitE Repeater Interface Controller | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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July 1993
DP83955A DP83956A LERICTM
LitE Repeater Interface Controller
General Description
The DP83955 56 LitE Repeater Interface Controller Specifications enclosed describe both the DP83955 and the
(LERIC) may be used to implement an IEEE 802 3 multiport DP83956 unless otherwise noted
repeater unit It fully satisfies the IEEE 802 3 repeater speci-
fication including the functions defined by the repeater seg-
ment partition and jabber lockup protection state machines
For IEEE 802 3 multiport repeater applications which re-
quire conformance to the IEEE 802 3 Draft Repeater Man-
agement options the DP83950 Repeater Interface Control-
The LERIC has an on-chip phase-locked-loop (PLL) for ler (RICTM) is recommended especially for highly-managed
Manchester data decoding a Manchester encoder and an hub requirements
Elasticity Buffer for preamble regeneration
Each LERIC can connect up to 7 cable segments via its Features
network interface ports One port is fully Attachment Unit Y Compliant with the IEEE 802 3 Repeater Specification
Interface (AUI) compatible and is able to connect to an ex- Y 7 network connections (ports) per chip
ternal Medium Attachment Unit (MAU) using the maximum
length of AUI cable The other 6 ports have integrated
10BASE-T transceivers These transceiver functions may
be bypassed so that the LERIC may be used with external
transceivers such as National’s DP8392 coaxial transceiv-
er In addition large repeater units may be constructed by
cascading LERICs together over the Inter-LERICTM or Inter-
RICTM bus
Y Selectable on-chip twisted-pair transceivers
Y Cascadable for large multiple RIC LERIC hub
applications
Y Compatible with AUI compliant transceivers
Y On-chip Elasticity Buffer Manchester encoder and
decoder
Y Separation Partition state machines for each port
The LERIC is configurable for specific applications It pro- Y Provides port status information for LED displays
vides port status information for LED array displays Addi-
including receive collision partition polarity and link
tionally the LERIC has a mP interface to provide individual
status
port status configuration and port enable disable func- Y Power-up configuration options Repeater and Partition
tions
Specifications Transceiver Interface Status Display
The
that
DP83956 has
two of the
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for
repeater
management
changed to unidirectional signals on DP83956 and one
and port disable
more signal is added to DP83956 to accommodate the addi- Y Per port receive squelch level selection
tion of bus transceivers for cascading a greater number of Y CMOS process for low power dissipation
LERICs in large repeater applications
Y Single 5V supply
1 0 System Diagram
Simple LERIC Hub
DataShee
TRI-STATE is a registered trademark of National Semiconductor Corporation
Inter-LERICTM Inter-RICTM LERICTM and RICTM are trademarks of National Semiconductor Corporation
PAL is a registered trademark of and used under license from Advanced Micro Devices Inc
GAL is a registered trademark of Lattice Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 11240
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2 0 Connection Diagrams (Continued)
Pin Name
TX4a
TX4b
GND
VCC
TX5b
TX5a
CD5b
CD5a
RX5b
RX5a
GND
VCC
RXI6a
RXI6b
TXO6Pa
TXO6b
TXO6a
TXO6Pb
GND
VCC
TXO7Pb
Pin Table for DP83955
(Configured as Port 1 Full AUI Ports 2 – 5 AUI and Ports 6 – 7 Twisted-Pair)
Pin No
Pin Name Pin No
Pin Name
Pin No
Pin Name
1
TXO7a
22
RXM
43 TX2a
2
TXO7b
23
IRD
44 TX2b
3
TXO7Pa
24
IRC
45 GND
4 RXI7a 25 STR
5 RXI7b 26 DFS
46 VCC
47 TX3b
6 GND
27
BUFEN
48
TX3a
7 VCC
8 IRE
28 ACKO 49 CD3b
29 CD1a 50 CD3a
9 ACTN 30 CD1b 51 RX3b
10
ANYXN
31
RX1a
52
RX3a
11 COLN 32 RX1b 53 GND
12 D7
13 D6
33 VCC
34 GND
54 VCC
55 CLK
14 D5
35 TX1a 56 MLOAD
15 D4
36 TX1b 57 WR
16 D3
37 GND
58 RD
17 D2
18 D1
38 VCC
59 ACKI
39 RX2b 60 RX4b
19 D0
40 RX2a 61 RX4a
20 VCC
21 GND
41 CD2a
D42ataSheetC4DU2b.com
62
63
CD4a
CD4b
Pin No
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
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3 0 Pin Description
Pin Name
Driver
Type
IO
Description
NETWORK INTERFACE PINS (On-Chip Transceiver Mode)
RXI2b to RXI7b
TP I Twisted-Pair Receive Input Negative
RXI2a to RXI7a
TP I Twisted-Pair Receive Input Positive
TXOP2b to TXOP7b
TT
O Twisted-Pair Pre-Emphasis Transmit Output Negative
TXO2b to TXO7b
TT O Twisted-Pair Transmit Output Negative
TXO2a to TXO7a
TT O Twisted-Pair Transmit Output Positive
TXOP2a to TXOP7a
TT
O Twisted-Pair Pre-Emphasis Transmit Output Positive
CD1a
AL I AUI Collision Detect Input Positive
CD1b
AL I AUI Collision Detect Input Negative
RX1a
AL I AUI Receive Input Positive
RX1b
AL I AUI Receive Input Negative
TX1a
AD O AUI Transmit Output Positive
TX1b
AD O AUI Transmit Output Negative
NETWORK INTERFACE PINS (External Transceiver Mode AUI Signal Level Compatibility Selected)
TX2a to TX7a
AL O Transmit Output Positive
TX2b to TX7b
AL O Transmit Output Negative
CD2a to CD7a
AL I Collision Input Positive
CD2b to CD7b
AL I Collision Input Negative
RX2a to RX7a
AL I Receive Input Positive
RX2b to RX7b
AL I Receive Input Negative
CD1a
CD1b
AL I AUI Collision Detect Input Positive
AL DaItaSheet4UAU.cI Coomllision Detect Input Negative
RX1a
AL I AUI Receive Input Positive
RX1b
AL I AUI Receive Input Negative
TX1a
AD O AUI Transmit Output Positive
TX1b
AD O AUI Transmit Output Negative
Note AD e AUI level and Drive compatible
TP e Twisted-Pair interface compatible
AL e AUI Level compatible
TT e TTL compatible
I e Input
O e Output
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11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DP83956A.PDF ] | |
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