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PDF IP175A Data sheet ( Hoja de datos )
| Número de pieza | IP175A | |
| Descripción | 5 Port 10/100 Ethernet Integrated Switch | |
| Fabricantes | IC Plus | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de IP175A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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IP175A LF
Preliminary Data Sheet
5 Port 10/100 Ethernet Integrated Switch
Features
General Description
5 port 10/100 Ethernet switch with built in IP175A LF is a low cost 10/100 Ethernet single
transceivers and memory
chip switch. It integrates a 5-port switch controller,
Build in SSRAM for frame buffer
SSRAM, and 5 10/100 Ethernet transceivers.
Built in storage of 1K MAC address
Each of the transceivers complies with the
Support flow control
IEEE802.3, IEEE802.3u, and IEEE802.3x
– Support IEEE802.3x for flow control for full specifications. The transceivers are designed in
duplex mode operation
DSP approach with 0.25um technology; they have
– Support backpressure for flow control for high noise immunity and robust performance.
half duplex mode operation
5 port switching fabric
IP175A LF operates in store and forward mode. It
– Support two-level hashing algorithm to supports flow control, auto MDI/MDI-X, CoS, port
solve MAC address collision
base VLAN, and LED functions, etc. Each port can
– Support MAC address aging
be configured to auto-negotiation or forced
– Store and forward mode
10M/100M, full/half duplex, and it is also able to
– Broadcast storm protection
configure to 100BaseFX transmission mode.
– Full line speed capability of 148800 (14880) Using an EEPROM or pull up/down resistors on
packets/sec for 100M (10M)
specified pins can configure the desired options.
– Support 1536 byte data transfer for VLAN IP175A LF does not support “forced 10M half
packet traffic
mode”.
– Port base VLAN
– Port base CoS configuration
DataSheet4IUP1.c7o5mA LF supports two MII ports for router
Integrate 5 ports transceiver
application, which supports 4 LAN ports and one
– Each port can be auto negotiable or forced WAN port. MII0 is for LAN traffic and MII1 is for
10M/100M, full/half duplex
WAN traffic and no external PHY is needed. Both
– Each port can be configured as 100BaseFX MII can work in PHY mode and interface to the
– Automatic MDI/MDI-X configuration
external MAC in this application. The external
Support two MII, one SMI and extended MII MAC can monitor or configure IP175A LF by
registers for router application
accessing MII registers through SMI.
Built in regulator for 3.3v to 2.15v
LED status of Link, activity, Full/half duplex, MII0 also can be configured to be MAC mode. It is
speed, and power on diagnostic function
used to interface an external PHY to work as a
Initial parameter setting by pin or EEPROM 4+1 switch.
(24LC01) configuration
Utilize single clock source (25Mhz)
0.25u technology
Support Lead Free package (Please refer to
the Order Information)
DataShee
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IP175A LF-DS-R07
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Applications (continued)
Application 2: 4 LAN port + one WAN port (Router)
R outer
IP 175A LF
5 port
sw itch controller
(PH Y m ode M II)
M II0
PHY
0
PHY
1
PHY
2
PHY
3
PHY
4
M II1
IP175A LF
Preliminary Data Sheet
MAC1
CPU
MAC2
4 X LAN port
E th e rn e t
PC
1 W AN port
E th e rn e t
ADSL
or
C able m odem
W AN to ISP
et4U.com
Application 3: 4 TP port + one external PHY
Switch
IP175A LF
5 port
switch controller
DataSheet4U.com
(MAC mode MII)
MII0
PHY
0
PHY
1
PHY
2
PHY
3
PHY
4
EXT
PHY
Use 4 builtin PHY (0~3).
Use MII0 port to connected
the external PHY.
DataShee
4 TP port
one external
PHY port
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IP175A LF
Preliminary Data Sheet
Pin Descriptions (continued)
Pin no.
Label
Type
Description
External MII1 interface (PHY mode only, P4EXT=1)
62
MII1_TXCLK
O MII Transmit clock
61, 60,
59, 58
TXD1_0, TXD1_1, IPL2 MII transmit data
TXD1_2, TXD1_3
It is sampled at the rising edge of MII1_TXCLK.
57 TXEN1
IPL2 MII transmit enable
69 COL1
It is used to frame TXD1[3:0]. It is sampled at the rising edge of
MII1_TXCLK.
O MII collision
63 RXDV1
It is active when PHY4 is set to be half duplex and a collision
event happens.
O MII receive data valid
67, 66,
65, 64
68
RXD1_0, RXD1_1, O
RXD1_2, RXD1_3
MII1_RXCLK
O
It is used to frame RXD1[3:0]. It is sent out at the falling edge of
MII1_RXCLK.
MII receive data
It is sent out at the falling edge of MII1_RXCLK.
MII DreacteaiSvehecelot4cUk .com
DataShee
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IP175A.PDF ] | |
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