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PDF IP175C Data sheet ( Hoja de datos )

Número de pieza IP175C
Descripción 5 Port 10/100 Ethernet Integrated Switch
Fabricantes IC Plus 
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IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
5 Port 10/100 Ethernet Integrated Switch
Features
General Description
IP175A PCB compatible (pins compatible)
IP175C/IP175CH integrates a 6-port switch
Built in 6 MAC and 5 PHY
controller, SSRAM, and 5 10/100 Ethernet
Each port can be configured to be 10Base-T, transceivers. Each of the transceivers complies
100Base-TX
with the IEEE802.3, IEEE802.3u, and IEEE802.3x
2k MAC address
specifications. The DSP approach is utilized for
Support auto-polarity for 10Mbps
designing transceivers with 0.18um technology;
Filter/ forward reserved address option
they have high noise immunity and robust
Broadcast storm protection
performance.
Auto MDI-MDIX
Support three MII/RMII ports
IP175C/IP175CH operates in store and forward
Support SMI with MDC up to 12.5 Mhz
mode. It supports flow control, auto MDI/MDI-X,
Support tagging & un-tagging
CoS, port base VLAN, bandwidth control, DiffServ,
Support Port base VLAN & tag VLAN
SMART MAC and LED functions, etc. Each port
Support CoS
can be configured to auto-negotiation or forced
Support port security option
10M/100M, full/half duplexmode. Using an
Support SMART MAC function
EEPROM or pull up/down resistors on specified
Support spanning tree protocol
pins can configure the desired options.
Max packet length 1552/ 1536 bytes
Support 8-level bandwidth control
Besides a 5-port switch application,
Support
Support
Link quality
direct, serial
LaEndD dfoural1c0o0lMorbmpsodDeaLtEaSDheet4IrUPou1.ct7eo5rmCa/IpPp1li7c5aCtioHn,suwphpiocrhts
three MII/RMII ports for
supports 4 LAN ports,
Support one fiber port with far end fault one WAN port and one HOME/PNA or Access
function for IP175CH only
point. The external MAC can monitor or configure
Built in linear regulator control circuit
IP175C/IP175CH by accessing MII registers
Low power consumption
through SMI0.
0.18um, 128-pin PQFP
Support Lead Free package (Please refer to MII/RMII port also can be configured to be MAC
the Order Information)
mode. It is used to interface an external PHY to
work as a 5+1 switch. Through SMI1
Note – some features need CPU support, please IP175C/IP175CH can monitor and configure
refer to the detail description inside this data sheet external PHY.
IP175CH supports one fiber port with far end fault
function
DataShee
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IP175C/IP175CH-DS-R13

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IP175C pdf
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IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Revision History
Revision #
IP175C-DS-R12
Change Description
1. Change to EEPROM register 14~18 or MII register 19~21 on page 32
2. Add SERIAL_LED_MODE to Pin diagram on page 6
3. Add pin 112 description for SERIAL_LED_MODE on page 27
4. Add PHY_31_REG_5[1] SERIAL_LED_MODE on page 97
5. Add SERIAL_LED_MODE = 0 on page 50
6. Add description for SERIAL_LED_MODE selection on page 50
7. Change MII0 MAC mode PHY address to 00000 on page 36
8. Change P4_FORCE_100 from 22.4 to 20.4 on page 36
IP175Cx-DS-R12.1 1.
2.
3.
4.
5.
6.
7.
8.
Replace IP175C with IP175C/IP175CH
Add “IP175CH support one fiber “ to feature list and general description on page
1
Modify Comparison Table on page 6 for IP175CH only
Add IP175CH Pin diagram on page 8
Add FXSD4 Pin description on page 30
Add “Fiber mode of port 4 (for IP175CH only)” function description on page 56
Modify Order Information on page 111
Add Fiber I/O Electrical Characteristics on page 102
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IP175C arduino
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IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Router application using two-MII/RMII ports (another option)
p4ext
1
mii1_dis mii2_en
00
p4mii_sni
0
rmii_en
x
mii0_mac_mod mii1_phy_mod
00
Switch Engine
MAC 5
MAC 0
PHY 0
MAC 1
PHY 1
MAC 2
PHY 2
MAC 3
PHY 3
MAC 4
X
PHY 4
MII0 / RMII0
MII1 / RMII1
Access Point /
HomePNA/
VOIP
CPU
TP
Note: PHY4 is disable and MII1/RMII1 is mac mode in
this application.
et4U.com
Router application using three-MII/RMII ports
p4ext
1
mii1_dis
0
mii2_en
1
p4mii_DsnaitaShermeti4i_Ue.ncom mii0_mac_mod mii2_mac_mod
0x
0
0
Switch Engine
MAC 5
MAC 0
PHY 0
MAC 1
PHY 1
MAC 2
PHY 2
MAC 3
PHY 3
MAC 4
X
PHY 4
MII0 / RMII0
MII2 / RMII2
MII1 / RMII1
Access Point /
HomePNA/
VOIP
CPU
DataShee
TP Note: PHY4 is an independent PHY in this application
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