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PDF EK7606 Data sheet ( Hoja de datos )

Número de pieza EK7606
Descripción 240 Output Analog Source Driver For av Application Cof / Cog
Fabricantes Eureka Microelectronics 
Logotipo Eureka Microelectronics Logotipo



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No Preview Available ! EK7606 Hoja de datos, Descripción, Manual

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֮ٙټጠʳ ˗ˢ˖ʳ˧˼̇˿˸ʳ Κʳ
ʳ
EK7606C PRELIMINARY DATA SHEETʳ
֮ٙᒳᇆʳ ˗ˢ˖ʳˡˢʳ Κ˧˗˦ˊˉ˃ˉ˖ˀ˃˄ʳ
ठʳ ءʳ ʳ ˥˘˩ʳ Κʳ ˃ˁ˄ʳ
଄ʳ ʳ ڻʳ ˣ˴˺˸ʳ Κʳ ʳ ˄ʳ˂ʳ˄ʳ
֮ٙࠫ˂ଥૡԫᥦ।ʳ ˥˸̉˼̆˼̂́ʳ˛˼̆̇̂̅̌ʳ
ठءʳ ଥૡֲཚʳ سயֲཚʳ
˥˘˩ˁʳ ˥˘˩ʳ˗˴̇˸ʳ ˘˹˹ˁʳ˗˴̇˸ʳ
˃ˁ˄ʳ ˅˃˃ˆ˂˃ˊ˂˃ˌʳ ˅˃˃ˆ˂˃ˊ˂˄ˈʳ
ଥૡ଄ڻʳ
˥˘˩ˁʳˣ˴˺˸ʳ
ʳ
ࠫ˂ଥૡႈؾ˂ʳ փ୲ʳ
˥˸̉˼̆˸ʳ˼̇˸̀ʳ˂ʳ˖̂́̇˸́̇ʳ
ˡ˸̊ʳ˜̆̆̈˸ʳ
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CONFIDENTIAL

1 page




EK7606 pdf
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EUREKA
3. BLOCK DIAGRAM
QA1 QB1 QC1 QA2
INH
++++
EK7606C
QA80 QB80 QC80
+++
Q1H
Q2H
VA (R)
VB (G)
VC (B)
TEST2
SHA SHB
SHA SHB
SHA SHB
SHA SHB
SHA SHB
SHA SHB
SHA SHB
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L/R
CPH1
CPH3
MODE
STH1
Clock
MUX
SR
SR SR SR
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Fig. 1 Block diagram
SR SR SR STH2
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z Clock MUX
Selects if the sampling is simultaneous or sequential. Also gates the clock.
z 3 x 80-bit bi-directional shift register
Generates enable signals for sequential sampling 134/160 groups of 3 input colors.
z Line control
Select sample circuit SHA or SHB and the high impedance output state
z SH control MUX
Select which sample and hold circuit samples the analog input value.
z AMUX
According to the controls signals, selects which input color goes to which group of outputs.
z Sample and hold Circuit (SHA, SHB)
Sample the input voltage when the enable signal of the shift register is generated and hold this value
IALuntil it is stored on the panel.
Tz Buffers
ENDrive the sample grayscale voltage on the panel.
CONFIDJuly 2003
- 4 - Preliminary Rev. 0.1
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EK7606 arduino
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EUREKA
EK7606C
et4U.com
CPH1
CPH2
CPH3
STH1
VA
VB
VC
1234
1234
1234
A1 A2 A3
B1 B2 B3
C1 C2 C3
78 79 80 81
78 79 80 81
78 79 80 81
A78 A79 A80
B78 B79 B80
C78 C79 C80
STH2
L/R = H shift from left to right
CPH2, CPH3 : clock input
MODE = L when TEST2 = L OR
Q1H = H or Q2H = H when TEST2 = H
Fig. 5 x1 sequential sampling mode
Each input is sampled sequentially synchronised with the associated rising edge of the corresponding
clock. CPH1 controls the sample for QAx outputs, CPH2 controls the sample for QBx outputs and CPH3
controls the sample for QCx outputs.
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Output enable signal is generated at the falling edge of the 80th period of CPH1 since the start pulse.
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July 2003
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CONFIDENTIAL- 10 -
Preliminary Rev. 0.1

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