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Número de pieza | EK7603 | |
Descripción | 480 / 402 Output Analog Source Driver For av Application Cog | |
Fabricantes | Eureka Microelectronics | |
Logotipo | ||
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֮ٙټጠ DOC Title Κ
EK7603 Data Sheet
֮ٙᒳᇆ DOC NO ΚTPL7603-0˄
ठ ء REV Κ0.2
ڻ Page Κ ˄ / ˄
֮ٙࠫ/ଥૡԫᥦ। Revision History
ठء
REV.
0.˄
0.2
ଥૡֲཚ
REV Date
2003/˄/27
2003/6/5
سயֲཚ
Eff. Date
2003/3/20
2003/6/˄7
ଥૡڻ
REV. Page
P.5
ࠫ/ଥૡႈؾ/ փ୲
Revise item / Content
New Issue
˄. OSEL = H or open Æ H
OSEL = L Æ L or open
2. When EDGSL = L Æ L or open
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CONFIDENTIAL
1 page www.DataSheet4U.com
EUREKA
3. BLOCK DIAGRAM
EK7603
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z Clock MUX
Fig. 1 Block diagram
Selects if the sampling is simultaneous or sequential. Also gates the clock.
z 3 x 134/160-bit bi-directional shift register
Generates enable signals for sequential sampling 134/160 groups of 3 input colors.
z Line control
Select sample circuit SHA or SHB and the high impedance output state
z SH control MUX
Select which sample and hold circuit samples the analog input value.
z AMUX
According to the controls signals, selects which input color goes to which group of outputs.
z Sample and hold Circuit (SHA, SHB)
Sample the input voltage when the enable signal of the shift register is generated and hold this value
IALuntil it is stored on the panel.
Tz Buffers
ENDrive the sample grayscale voltage on the panel.
CONFIDJune 2003
- 4 - Preliminary Rev. 0.2
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EUREKA
5.5 Relationship between OE and output waveform
EK7603
Fig. 6 OE timing diagram
At OE rising/falling edge, the sample voltages are output on the panel. As long as OE is active, the
402/480 output buffers are forced in a high impedance state.
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June 2003
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CONFIDENTIAL-10 -
Preliminary Rev. 0.2
11 Page |
Páginas | Total 16 Páginas | |
PDF Descargar | [ Datasheet EK7603.PDF ] |
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