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PDF 182A934 Data sheet ( Hoja de datos )
| Número de pieza | 182A934 | |
| Descripción | 32K x 8 Radiation Hardened Static RAM | |
| Fabricantes | Bae Systems | |
| Logotipo |  |
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32K x 8
Radiation Hardened
Static RAM – 5 V
167A690
182A934
Features
Product Description
Radiation
• Fabricated with Bulk CMOS 0.8 µm Process
• Total Dose Hardness through 1x106 rad(Si)
• Neutron Hardness through 1x1014 N/cm2
• Dynamic and Static Transient Upset Hardness
through 1x109 rad(Si)/s
• Soft Error Rate of < 1x10-11 Upsets/Bit-Day
• Dose Rate Survivability through 1x1012 rad(Si)/s
• Latchup Free
Other
• Read/Write Cycle Times ≤30 ns (-55 °C to 125°C)
• SMD Number 5962H92153
• Asynchronous Operation
• CMOS or TTL Compatible I/O
• Single 5 V ±10% Power Supply
• Low Operating Power
• Packaging Options
• 36-Lead Flat Pack (0.630” x 0.650”)
• 28-Lead DIP, MIL-STD-1835, CDIP2-T28
General Description
DataSheet4U.com
The 32K x 8 radiation hardened static RAM is a
high performance, low power device designed
and fabricated in 0.8 µm Radiation Hardened
Complementary Metal Oxide Semiconductor
(RHCMOS) technology. BAE SYSTEMS’ device
is designed for radiation environments using
industry standard functionality. The memory can
be personalized for either CMOS or Transistor
Transistor Logic (TTL) input receivers. The
SRAM operates over the full military temperature
range and requires a single 5 V ±10% power
supply. Power consumption is typically less than
20 mW/MHz in operation, and less than 10 mW in
the low power disabled mode. The SRAM read
operation is fully asynchronous, with an
associated typical access time of 20
nanoseconds.
BAE SYSTEMS’ bulk CMOS technology achieves
radiation hardening via a combination of process
technology enhancements and specific circuit
improvements.
DataShee
DataSheet4U.com
DataSheet4 U .com
BAE SYSTEMS • 9300 Wellington Road • Manassas, Virginia 20110-4122
1 page  
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Read Cycle AC Timing Characteristics(1)
et4U.com
Test
Read Cycle Time
Address Access Time
Output Hold After Address Change
Chip Select Access Time
Chip Select to Output Active
Chip Select to Output Disable
Chip Enable Access Time
Chip Enable to Output Active
Chip Disable to Output Disable
Output Enable Access Time
Output Enable to Output Active
Output Enable to Output Disable
Symbol
tAVAV
tAVQV
tAXQX
tSLQV
tSLQX
tSHQZ
tEHQV
tEHQX
tELQZ
tGLQV
tGLQX
tGHQZ
Minimum or
Maximum
Minimum
Worst Case By Speed
-30 -40 -60
30 40 60
Maximum
30
40 60
Minimum
5
55
Maximum
30
40 60
Minimum
Maximum
Maximum
3
CMOS - 10
TTL - 12
30
3
15
40
3
15
60
Minimum
Maximum
Maximum
Minimum
Maximum
33
CMOS - 10
TTL - 12
15
CMOS - 12 CMOS - 15
TTL - 15 TTL - 18
33
CMOS - 10
TTL - 12
15
3
15
15
3
15
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
1)Test conditions: input switching levels VIL/VIH = 0.5 V/VDD -0.5 V (CMOS), VIL/VIH = 0 V/3 V (TTL), input rise
and fall times < 5 ns, input and output timing reDfearteanSceheleevte4lUs .schoomwn in the Tester AC Timing Characteristics
table, capacitive output loading CL = 50 pF. For CL > 50 pF, derate access times by 0.02 ns/pF (typical).
-55 °C ≤ Tcase ≤ +125°C; 4.5 V ≤ VDD ≤ 5.5 V; unless otherwise specified.
Read Cycle Timing Diagram
Address
S
E
G
DataSheet4U.com
Data
Out
DataSheet4 U .com
tAVAV
Valid Address
tAVQV
tSLQV
tSLQX
tEHQV
tEHQX
tGLQV
tGLQX
High Impedance
5
Valid Data
tAXQX
tSHQZ
tELQZ
tSHQZ
DataShee
5 Page 
www.DataSheet4U.com
Packaging
The 32K x 8 SRAM is offered in a custom 36-lead FP,
36-lead FPP or standard 28-lead DIP. All packages are
constructed of multilayer ceramic (AI2O3) and feature
internal power and ground planes. The FP also features
a non-conductive ceramic tie bar on the lead frame.
The purpose of the tie bar is to allow electrical testing of
the device, while preserving the lead integrity during
shipping and handling, up to the point of lead forming
and insertion.
Optional capacitors can be mounted to the package to
maximize supply noise decoupling and increase board
packing density. These capacitors attach directly to the
internal package power and ground planes. This design
minimizes resistance and inductance of the bond wire
and package, both of which are critical in a transient
radiation environment. All NC pins must be connected to
either VDD, GND or an active driver to prevent charge
build up in the radiation environment. (NC = no connect.)
36-Lead Flat Pack Pinout
28-Lead DIP Pinout
et4U.com
GND
VDD
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
NC
VDD
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Top
View
36-Lead Flat Pack
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
Lead 1
H
F
(2)
Lead 18
(1)
JM
A
P
Lead 1 Indicator
K VDD
VDD
GND
GND
N
Q
R
GND
GND
VDD
VDD
DataSheet4U.com
GND
VDD
W
E
A13
A8
A9
A11
G
A10
S
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
GND
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7 Top
8 View
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
W
A13
A8
A9
A11
G
A10
S
DQ7
DQ6
DQ5
DQ4
DQ3
DataSheet4U.com
DataShee
Lead 36
Lead 19
L
B
(Width)
E
(Pitch)
C
A=.085 ± .010
B=.008 ± .002
C=.013 ± .004
D=.650 ± .010
E=.025 ± .002
F=.630 ± .007
G=.425 ± .004
H=1.490
J=.135
K=.080
L=.020
M=.285
N=.100
P=.040
Q=.130
R=.260
Notes:
1) Part mark per device specification.
2) “QML” may not be required per device
specification.
3) Dimensions are in inches.
4) Lead width: .008 ± .002.
5) Lead height: .006 ± .002.
6) Unless otherwise specified, all
tolerances are ± .005”.
11
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11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet 182A934.PDF ] | |
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