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PDF TE28F128J3D Data sheet ( Hoja de datos )
| Número de pieza | TE28F128J3D | |
| Descripción | Embedded Flash Memory | |
| Fabricantes | Intel | |
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Intel® Embedded Flash Memory (J3 v. D)
(32, 64, and 128 Mbit)
Datasheet
Product Features
■ Architecture
— High-density symmetrical 128-Kbyte
blocks
—128 Mbit (128 blocks)
—64 Mbit (64 blocks)
—32 Mbit (32 blocks)
■ Performance
— 75 ns Initial Access Speed (128/64/32
-Mbit densities)
— 25 ns 8-word and 4-word
Asynchronous page-mode reads
— 32-Byte Write buffer
—4 μs per Byte Effective
programming time
■ Security
— Enhanced security options for code
protection
— 128-bit Protection Register
—64-bit Unique device identifier
—64-bit User-programmable OTP cells
— Absolute protection with VPEN = GND
— Individual block locking
— Block erase/program lockout during
power transitions
■ Software
— Program and erase suspend support
— Flash Data Integrator (FDI), Common
Flash Interface (CFI) Compatible
■ S——ysVVteCCmCCQ=V=o2l.2t7a.7gVeVtaotno3d.36P.6VoVweDr ataSheet4U.c■omQ—u-Oa4lp0itey°rCaatintnodg+Rt8eem5li°paCebrialtiutyre:
— 100K Minimum erase cycles per block
— 0.13 μm ETOX™ VIII Process
■ Packaging
— 56-Lead TSOP package
— 64-Ball Intel® Easy BGA package
The Intel® Embedded Flash Memory J3 Version D (J3 v. D) provides improved mainstream performance
with enhanced security features, taking advantage of the high quality and reliability of the NOR-based Intel
0.13 μm ETOX™ VIII process technology. Offered in 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit
densities, the J3 v. D device brings reliable, low-voltage capability (3 V read, program, and erase) with high
speed, low-power operation.
The J3 v. D device takes advantage of the proven manufacturing experience and is ideal for code and data
applications where high density and low cost are required, such as in networking, telecommunications,
digital set top boxes, audio recording, and digital imaging.
Intel Flash Memory components also deliver a new generation of forward-compatible software support. By
using the Common Flash Interface (CFI) and Scalable Command Set (SCS), customers can take advantage
of density upgrades and optimized write capabilities of future Intel® Flash Memory devices.
Notice: This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the
latest datasheet before finalizing a design.
308551- 003
Feburary 2006
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Revision History
Date of Revision
July 2005
September 2005
February 2006
Version
001
002
003
Description
- Initial release
- Marketing name was changed from 28FxxxJ3 to J3 v. D
- Table 18 “Command Bus Operations for J3 v. D” on page 37 was updated
- Section 9.2.2, “Read Status Register” on page 40
- Section 9.3.2, “Buffered Programming” on page 42
- Table 27 “Valid Commands During Suspend” on page 44
- Table 28 “STS Configuration Register” on page 45 was added
- Section 5.3.1, “Power-Up/Down Characteristics” on page 20 was modified
- Notes on Table 8 “DC Voltage Characteristics” on page 22 were updated
- Table 10 “Read Operations” on page 25 was updated with R16 Value
- Table 12 “Configuration Performance” on page 30 was updated
- Note 1 of Table 29 “STS Configuration Coding Definitions” on page 46 was
updated
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2.2 Memory Map
Figure 2. J3 v. D Memory Map
0FFFFFF
0FE 0 0 0 0
A [23-0]:128 Mbit
A [22-0]: 64 Mbit
A [21-0]: 32 Mbit
128-Kbyte Block 127
7FFFFF
7 F0 0 0 0
A [23-1]: 128 Mbit
A [22-1]: 64 Mbit
A [21-1]: 32 Mbit
64-Kword Block 127
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0 7FFFFF
0 7E 0 0 0 0
128-Kbyte Block 63
3FFFFF
3 F0 0 0 0
64-Kword Block 63
0 3FFFFF
0 3E 0 0 0 0
128-Kbyte Block 31
1FFFFF
1 F0 0 0 0
64-Kword Block 31
0 0 3FFFF
0020000
0 0 1FFFF
0000000
128-Kbyte Block 1
0 1FFFF
128-Kbyte BlDocakta0Sheet4U.co0001mF0F0F0F0
000000
Byte-Wide (x8) Mode
64-Kword Block 1
64-Kword Block 0
Word Wide (x16) Mode
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| PDF Descargar | [ Datasheet TE28F128J3D.PDF ] | |
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