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PDF DJLXT971ALCA4S Data sheet ( Hoja de datos )
| Número de pieza | DJLXT971ALCA4S | |
| Descripción | Dual Speed Fast Ethernet PHY Transceiver | |
| Fabricantes | Intel | |
| Logotipo |  |
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Intel® LXT971A
3.3V Dual-Speed Fast Ethernet PHY Transceiver
Datasheet
The LXT971A is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both
100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII) for
easy attachment to 10/100 Media Access Controllers (MACs). The LXT971A also provides a
Low Voltage PECL (LVPECL) interface for use with 100BASE-FX fiber networks.
This document also supports the LXT971 device.
The LXT971A supports full-duplex operation at 10 Mbps and 100 Mbps. Its operating condition
can be set using auto-negotiation, parallel detection, or manual control.
The LXT971A is fabricated with an advanced CMOS process and requires only a single 3.3V
power supply.
Applications
■ Combination 10BASE-T/100BASE-TX or ■ 10/100 PCMCIA Cards
100BASE-FX Network Interface Cards
(NICs)
■ Cable Modems and Set-Top Boxes
Product Features
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■ 3.3V Operation.
■ Low power consumption (300 mW
typical).
■ Low-power “Sleep” mode.
■ 10BASE-T and 100BASE-TX using a
single RJ-45 connection.
■ Supports auto-negotiation and parallel
detection.
■ MII interface with extended register
capability.
■ Robust baseline wander correction
performance.
■ 100BASE-FX fiber-optic capable.
■ Standard CSMA/CD or full-duplex
operation.
■ Supports JTAG boundary scan.
■ Configurable via MDIO serial port or
hardware control pins.
■ Integrated, programmable LED drivers.
■ 64-ball Plastic Ball Grid Array (PBGA).
— LXT971ABC - Commercial (0° to
70°C ambient).
— LXT971ABE - Extended (-40° to 85°C
ambient).
■ 64-pin Low-profile Quad Flat Package
(LQFP).
— LXT971ALC - Commercial (0° to
70°C ambient).
— LXT971ALE - Extended (-40° to 85°C
ambient).
DataShee
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Order Number: 249414-002
August 2002
1 page  
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LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
Figures
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LXT971A Block Diagram...................................................................................................9
64-Pin PBGA Pin Assignments.........................................................................................10
64-Pin LQFP Pin Assignments..........................................................................................11
Management Interface Read Frame Structure...................................................................21
Management Interface Write Frame Structure ..................................................................21
Interrupt Logic...................................................................................................................22
Initialization Sequence ......................................................................................................24
Hardware Configuration Settings ......................................................................................26
Link Establishment Overview ...........................................................................................28
10BASE-T Clocking .........................................................................................................30
100BASE-X Clocking .......................................................................................................30
Link Down Clock Transition.............................................................................................30
Loopback Paths .................................................................................................................31
100BASE-X Frame Format...............................................................................................32
100BASE-TX Data Path....................................................................................................33
100BASE-TX Reception with no Errors...........................................................................33
100BASE-TX Reception with Invalid Symbol .................................................................33
100BASE-TX Transmission with no Errors......................................................................34
100BASE-TX Transmission with Collision......................................................................34
Protocol Sublayers.............................................................................................................35
LED Pulse Stretching ........................................................................................................42
Typical Twisted-Pair Interface - Switch............................................................................45
Typical Twisted-Pair Interface - NIC................................................................................46
Typical MII InterfaceD.a...t.a..S...h..e..e..t..4..U....c..o..m............................................................................47
Typical Fiber Interface ......................................................................................................48
100BASE-TX Receive Timing - 4B Mode .......................................................................53
100BASE-TX Transmit Timing - 4B Mode......................................................................54
100BASE-FX Receive Timing..........................................................................................55
100BASE-FX Transmit Timing ........................................................................................56
10BASE-T Receive Timing ..............................................................................................57
10BASE-T Transmit Timing.............................................................................................58
10BASE-T Jabber and Unjabber Timing ..........................................................................59
10BASE-T SQE (Heartbeat) Timing.................................................................................59
Auto Negotiation and Fast Link Pulse Timing..................................................................60
Fast Link Pulse Timing .....................................................................................................60
MDIO Input Timing ..........................................................................................................61
MDIO Output Timing........................................................................................................61
Power-Up Timing..............................................................................................................62
RESET Pulse Width and Recovery Timing ......................................................................62
PHY Identifier Bit Mapping..............................................................................................68
PBGA Package Specification ............................................................................................79
LXT971A LQFP Package Specifications..........................................................................80
DataShee
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Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
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5
5 Page 
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 1. LXT971A Block Diagram
RESET
ADDR<4:0>
MDIO
MDC
MDINT
MDDIS
TX_EN
TXD<3:0>
TX_ER
TX_CLK
LED/CFG<3:1>
COL
RX_CLK
RXD<3:0>
RXDV
CRS
RX_ER
Management /
Mode Select
Logic
Register Set
Clock
Generator
Power Supply
Parallel/Serial
Converter
Manchester
Encoder
10
Scrambler 100
& Encoder
Register
Set
Auto
Negotiation
OSP™
Pulse
Shaper
Collision
Detect
Clock
Generator
Media
Select
Serial-to-
Parallel
Carrier Sense Converter
Data Valid
Error Detect
Manchester
10 Decoder
100
Decoder &
Descrambler
OSP™
Slicer
+
TP
Driver
-
+
ECL
Driver -
TP/Fiber
Out
OSP™
Adaptive EQ with
Baseline Wander
Cancellation
JTAG
+
100TX
-
+
100FX
-
+
10BT
-
TP/Fiber In
VCC
GND
PWRDWN
REFCLK
TxSLEW<1:0>
TPFOP
TPFON
TDIO
5 TMS
TCK
TRST
TPFIP
TPFIN
SD/TP
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DataShee
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Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
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