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PDF EP314 Data sheet ( Hoja de datos )
| Número de pieza | EP314 | |
| Descripción | (EP312 / EP314) Classic FPLDs | |
| Fabricantes | Altera | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de EP314 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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www.DataSheet4U.com
April 1995, ver. 1
®
EP312 & EP324
Classic EPLDs
Data Sheet
Features
General
Description
DataSheet4U.com
Altera Corporation
A-DS-312/324.01
DataSheet4 U .com
s High-performance EPLDs with 12 macrocells (EP312) or 24
macrocells (EP324)
– Combinatorial speeds as fast as 25 ns
– Counter frequencies of up to 33.3 MHz
– Pipelined data rates of up to 66 MHz
s Multiple 20-pin PAL and GAL replacement and integration
s Device erasure and reprogramming with advanced, nonvolatile
EPROM configuration elements
s Programmable registers providing D, T, JK, and SR flipflops with
individual Clear and Clock controls
s Dual feedback on all macrocells for implementing buried registers
with bidirectional I/O
s Programmable-AND/allocatable-OR structure allowing up to 16
product terms per macrocell
s Two product terms on all macrocell control signals
DataShee
s Programmable inputs (8 in EP312, 10 in EP324) configurable as
latches, rDegaitsateSrhs,eoert4flUow.c-othmrough input
s Available in windowed ceramic and one-time-programmable (OTP)
plastic packages with 24 to 44 pins:
– 24-pin ceramic and plastic dual in-line package (CerDIP and
PDIP)
– 28-pin plastic J-lead chip carrier (PLCC)
– 40-pin CerDIP and PDIP
– 44-pin PLCC
s One global Clock pin; one global Input Latch Enable/Input
Clock/Input (ILE/ICLK/INPUT) pin
s Programmable “standby” option for low-power operation
s Programmable Security Bit for total protection of proprietary designs
s 100% generically testable to provide 100% programming yield
s Software design support with the Altera PLDshell Plus software and
a wide range of third-party tools; programming support through
third-party vendors
The CMOS EPROM EP312 and EP324 devices have a versatile macrocell
structure and I/O architecture, which allow them to implement high-
performance logic functions effectively. The EP312 and EP324 input and
macrocell features are a superset of features offered by PAL/GAL
devices. Therefore, EP312 and EP324 devices can be used as an alternative
to multiple PAL/GAL devices, SSI and MSI logic devices, or low-end gate
arrays.
1
1 page  
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et4U.com
EP312 & EP324 Classic EPLDs
To implement registered functions, each macrocell register can be
individually programmed for D, T, JK, or SR operation. If necessary, the
register can be bypassed for combinatorial operation. The XOR gate can
implement active-high or active-low logic, or use DeMorgan’s inversion
to reduce the number of product terms required to implement a function.
Registers are cleared automatically during power-up.
The macrocell output can be fed back to the logic array via two paths. Pin
feedback that is connected after the output buffer can be used to
implement bidirectional I/O; if internal feedback is used for a buried
register or logic function, the pin feedback can be used as an input.
Product-Term Allocation
In EP312 and EP324 devices, product-term resources can be taken from
one macrocell and used in another. For product-term allocation,
macrocells in both the EP312 and EP324 are divided into 2 rings. The
EP312 has 6 macrocells per ring; the EP324 has 12 macrocells per ring.
Product terms from one macrocell can be allocated to adjacent macrocells
in the same ring. Product terms are allocated in groups of 4, and a
macrocell can borrow up to 8 product terms (4 from each adjacent
macrocell).
DataShee
Table 1 and TDaabtlaeS2hsheoewt4Uth.ecpormoduct-term allocation rings for the EP312
and EP324 devices, respectively. The Altera PLDshell Plus design
software automatically allocates product terms.
DataSheet4U.com
Altera Corporation
DataSheet4 U .com
5
5 Page 
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EP312 & EP324 Classic EPLDs
Absolute Maximum Ratings Note (1)
Symbol
Parameter
VCC
VI
TSTG
TAMB
Supply voltage
DC input voltage
Storage temperature
Ambient temperature
Conditions
Note (2)
Notes (2), (3)
Note (4)
Min Max Unit
–2.0
–0.5
–65
–10
7.0
VCC + 0.5
150
85
V
V
°C
°C
Recommended Operating Conditions
Symbol
Parameter
VCC Supply voltage
VIN Input voltage
VO Output voltage
TA Operating temperature
TA Operating temperature
tR Input rise time
tF Input fall time
Conditions
For commercial use
For industrial use
Min Max Unit
4.75
0
0
0
–40
5.25
VCC
VCC
70
85
500
500
V
V
V
°C
°C
ns
ns
et4U.comDC Operating Conditions Note (5)
DataShee
Symbol
Parameter
VIH High-level input voltage
VIL Low-level input voltage
VOH High-level TTL output voltage
VOH High-level CMOS output voltage
VOL Low-level output voltage
II Input leakage current
IOZ Tri-state output leakage current
ISC Output short-circuit current
Conditions
DataSheet4U.com
Note (2)
Note (2)
IOH = –4.0 mA DC, VCC = min.
IOH = –2 mA DC, VCC = min.
IOL = 8 mA DC, VCC = min.
VCC = max., GND < VIN < VCC
VCC = max., GND < VOUT < VCC
VCC = max., VOUT = 0.5 V, Note (6)
Min
2.0
–0.3
2.4
3.84
–30
Max
VCC + 0.3
0.8
0.45
10
10
–90
Unit
V
V
V
V
V
µA
µA
mA
Capacitance Note (5)
Symbol
Parameter
CIN
COUT
CCLK
CCLK
CVPP
Input capacitance
I/O capacitance
EP312 ILE/ICLK/INPUT pin capacitance
EP324 ILE/ICLK/INPUT pin capacitance
VPP pin capacitance
Conditions
VIN = 0 V, f = 1.0 MHz
VOUT = 0 V, f = 1.0 MHz
VOUT = 0 V, f = 1.0 MHz
VOUT = 0 V, f = 1.0 MHz
Note (7), f = 1.0 MHz
Min Max Unit
8 pF
15 pF
12 pF
15 pF
25 pF
DataSheet4U.com
Altera Corporation
DataSheet4 U .com
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet EP314.PDF ] | |
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