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PDF TC59SM716AFT Data sheet ( Hoja de datos )

Número de pieza TC59SM716AFT
Descripción (TC59SM704 - TC59SM716) SDRAM
Fabricantes Toshiba 
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TC59SM716/08/04AFT/AFTL-70,-75,-80
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
2,097,152-WORDS × 4 BANKS × 16-BITS SYNCHRONOUS DYNAMIC RAM
4,194,304-WORDS × 4 BANKS × 8-BITS SYNCHRONOUS DYNAMIC RAM
8,388,608-WORDS × 4 BANKS × 4-BITS SYNCHRONOUS DYNAMIC RAM
DESCRIPTION
TC59SM716AFT/AFTL is a CMOS synchronous dynamic random access memory organized as 2,097,152-words ×
4 banks × 16 bits and TC59SM708AFT/AFTL is organized as 4,194,304 words × 4 banks × 8 bits and
TC59SM704AFT/AFTL is organized as 8,388,608 words × 4 banks × 4 bits. Fully synchronous operations are
referenced to the positive edges of clock input and can transfer data up to 143M words per second. These devices
are controlled by commands setting. Each bank are kept active so that DRAM core sense amplifiers can be used as
a cache. The refresh functions, either Auto Refresh or Self Refresh are easy to use. By having a programmable
Mode Register, the system can choose the most suitable modes which will maximize its performance. These devices
are ideal for main memory in applications such as work-stations.
FEATURES
PARAMETER
TC59SM716/M708/M704
-70 -75 -80
tCK Clock Cycle Time (min)
7 ns 7.5 ns 8 ns
tRAS Active to Precharge Command Period (min)
42 ns
45 ns
48 ns
tAC Access Time from CLK (max)
5.4 ns
5.4 ns
6 ns
tRC Ref/Active to Ref/Active Command Period (min)
57 ns
65 ns
68 ns
ICC1 Operation Current (max) (Single bank)
80 mA
75 mA
70 mA
ICC4 Burst Operation Current (max)
100 mA
95 mA
90 mA
ICC6 Self-Refresh Current (max)
2 mA
2 mA
2 mA
Single power supply of 3.3 V ± 0.3 V
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Up to 143 MHz clock frequency
Synchronous operations: All signals referenced to the positive edges of clock
Architecture:
Pipeline
Organization
TC59SM716AFT/AFTL: 2,097,152 words × 4 banks × 16 bits
TC59SM708AFT/AFTL: 4,194,304 words × 4 banks × 8 bits
TC59SM704AFT/AFTL: 8,388,608 words × 4 banks × 4 bits
Programmable Mode register
Auto Refresh and Self Refresh
Burst Length:
1, 2, 4, 8, Full page
CAS Latency:
2, 3
Single Write Mode
Burst Stop Function
Byte Data Controlled by L-DQM, U-DQM (TC59SM716)
4K Refresh cycles/64 ms
Interface:
LVTTL
Package
TC59SM716AFT/AFTL: TSOPII54-P-400-0.80B
TC59SM708AFT/AFTL: TSOPII54-P-400-0.80B
TC59SM704AFT/AFTL: TSOPII54-P-400-0.80B
980910EBA1
TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in
general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of
the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure
of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please
ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications.
Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
The products described in this document are subject to the foreign exchange and foreign trade laws.
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
The information contained herein is subject to change without notice.
DataSheet4U.com
2000-02-08 1/49
DataShee
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TC59SM716AFT pdf
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TC59SM716/08/04AFT/AFTL-70,-75,-80
DC CHARACTERISTICS (VCC = 3.3 V ± 0.3 V, Ta = 0°~70°C)
PARAMETER
OPERATING CURRENT
tCK = min, tRC = min
1 bank operation
Active Precharge command cycling
without burst operation
-70 -75 -80
SYMBOL
UNITS NOTES
MIN MAX MIN MAX MIN MAX
ICC1
80 75 70
3
STANDBY CURRENT
tCK = min, CS = VIH,
VIH/L = VIH(min) / VIL(max),
Bank: Inactive state
CKE = VIH
ICC2
CKE = VIL
(Power Down mode)
ICC2P
40 35 30
111
3
3
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STANDBY CURRENT
CLK = VIL, CS = VIH,
VIH/L = VIH(min) / VIL(max),
Bank: Inactive state
NO OPERATING CURRENT
tCK = min, CS = VIH(min),
Bank: Active state (4 banks)
CKE = VIH
ICC2S
CKE = VIL
(Power Down mode)
ICC2PS
CKE = VIH
ICC3
CKE = VIL
(Power Down mode)
ICC3P
10 10 10
111
mA
60 55 50
10 10 10
BURST OPERATING CURRENT
tCK = min
Read/Write command cycling
ICC4
100 95 90
AUTO REFRESH CURRENT
tCK = min, tRC = min
Auto Refresh command cycling
SELF REFRESH CURRENT
Self Refresh mode
CKE = 0.2 V
ICC5
170 160 150
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Standard Products
(AFT)
222
ICC6
Low Power Version
(AFTL)
800 800 800
µA
3, 4
3
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PARAMETER
INPUT LEAKAGE CURRENT
(0 V VIN VCC, all other pins not under test = 0 V)
OUTPUT LEAKAGE CURRENT
(Output disable, 0 V VOUT VCCQ)
LVTTL OUTPUT H LEVEL VOLTAGE (IOUT = −2 mA)
LVTTL OUTPUT L LEVEL VOLTAGE (IOUT = 2 mA)
SYMBOL
II(L)
IO(L)
VOH
VOL
MIN
5
5
2.4
MAX
5
5
0.4
UNITS NOTES
µA
µA
V
V
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2000-02-08 5/49

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TC59SM716AFT arduino
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TC59SM716/08/04AFT/AFTL-70,-75,-80
Control Timing of Input Data (TC59SM708/M704)
(Word Mask)
CLK
DQM
DQ0~DQ7
(DQ0~DQ3)*
tCMH
tCMS tCMH
tCMS
tDS tDH
Input
data valid
tDS tDH
Input
data valid
tDS tDH
Input
data valid
tDS tDH
Input
data valid
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(Clock Mask)
CLK
CKE
DQ0~DQ7
(DQ0~DQ3)*
tCKH
tCKS tCKH
tCKS
tDS tDH
Input
data valid
tDS tDH
Input
data valid
tDS tDH
Input
data valid
tDS tDH
Input
data valid
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Control Timing of Output Data (TC59SM708/M704)
(Output Enable)
CLK
DQM
DQ0~DQ7
(DQ0~DQ3)*
tCMH
tCMS tCMH
tCMS
tAC
tOH
tAC
tOH
Output
data valid
tHZ
tOH
Output
data valid
tAC
tLZ
Open
tAC
tOH
Output
data valid
DataShee
(Clock Mask)
CLK
tCKH
CKE
tAC
tOH
DQ0~DQ7
(DQ0~DQ3)*
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*: TC59SM704
tCKS tCKH
tAC
tOH
Output
data valid
tCKS
tAC
tOH
Output data valid
tAC
tOH
Output
data valid
2000-02-08 11/49
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