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PDF MAP-CA Data sheet ( Hoja de datos )
| Número de pieza | MAP-CA | |
| Descripción | Digital Signal Processor Chip | |
| Fabricantes | Equator Technologies | |
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Equator Hardware Reference
MAP-CA DSP
Datasheet
DataSheet4U.com
Equator Technologies, Inc.
June 20, 2001
Document Number: HWR.CA.DS.2001.06.20
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Table of Contents
iii
Introduction to the MAP-CA Digital Signal Processor Chip ..........................................xi
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Chapter 1 Architecture Overview .......................................................................................... 1
1.1 The VLIW Core.................................................................................................................... 2
1.1.1 Execution Units............................................................................................................. 2
1.1.1.1 I-ALU.................................................................................................................... 3
1.1.1.2 IG-ALU ................................................................................................................. 3
1.1.1.3 Simple Interlocks .................................................................................................. 3
1.1.1.4 Extensive Predication............................................................................................ 3
1.1.2 Register Resources........................................................................................................ 3
1.1.2.1 Global Registers .................................................................................................... 3
1.1.2.2 Breakpoint Registers ............................................................................................. 3
1.1.2.3 General Registers .................................................................................................. 3
1.1.2.4 Predicate Registers ................................................................................................ 3
1.1.2.5 PLC/PLV 128-bit registers.................................................................................... 4
1.2 Interrupts and Exceptions ............D..a..t.a..S..h..e..e..t.4..U....c..o..m................................................................ 4
1.2.1 Core Interrupts and Exceptions..................................................................................... 4
1.2.2 Interrupt Controller ....................................................................................................... 4
1.3 Timers................................................................................................................................... 5
1.4 Memory Hierarchy ............................................................................................................... 5
1.4.1 Caches........................................................................................................................... 5
1.4.2 Address Translation ...................................................................................................... 5
1.5 Databuses and Controllers .................................................................................................... 6
1.5.1 Memory Interface Controller ........................................................................................ 6
1.5.2 Data Transfer Switch (DTS) ......................................................................................... 6
1.5.3 DataStreamer DMA Controller..................................................................................... 6
1.5.4 PCI Bus ......................................................................................................................... 6
1.5.5 I/O Bus.......................................................................................................................... 7
1.6 Coprocessors......................................................................................................................... 7
1.6.1 VLx ............................................................................................................................... 7
1.6.2 Video Filter ................................................................................................................... 7
1.6.3 DES Module ................................................................................................................. 7
1.7 I/O Interfaces ........................................................................................................................ 8
1.7.1 Audio Interfaces............................................................................................................ 8
1.7.1.1 IEC958 Audio Interface ........................................................................................ 8
1.7.1.2 I2S Interface .......................................................................................................... 8
1.7.2 Video Interfaces............................................................................................................ 8
1.7.2.1 Transport Channel Interfaces ................................................................................ 8
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Equator Technologies, Inc.
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MAP-CA DSP Datasheet
June 20, 2001
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5 Page 
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List of Figures
ix
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Figure 1-1: MAP-CA DSP Block Diagram ..................................................................................... 1
Figure 1-2: The VLx Coprocessor .................................................................................................. 7
Figure 1-3: Display Refresh Controller ........................................................................................... 9
Figure 3-1: View of balls from the bottom ................................................................................... 13
Figure 3-2: MAP-CA DSP pins viewed from top ......................................................................... 16
Figure 4-1: MAP-CA DSP Interface ............................................................................................. 17
Figure 4-2: TAP State Transition Diagram ................................................................................... 30
Figure 4-3: Boundary Scan Block Diagram .................................................................................. 31
Figure 4-4: Device Identification Register .................................................................................... 31
Figure 5-1: 64-bit, 4MB configuration using ×32, 8Mb parts ...................................................... 35
Figure 5-2: 64-bit, 16 MB configuration using ×8, 16 Mb parts .................................................. 35
Figure 5-4: 64-bit, 64 MB configuration using ×16, 64 Mb parts ................................................ 36
Figure 5-3: 64-bit, 16 MB configuration using ×16 16Mb parts .................................................. 37
Figure 5-6: 64-bit, 128MB configurationDuastianSgh×ee1t64,U1.c2o8mMb parts .............................................. 37
Figure 5-5: 64-bit, 64MB configuration using ×16, 128Mb parts ................................................ 38
Figure 5-7: IEC958 Interface ........................................................................................................ 38
Figure 5-8: I2S Interface ................................................................................................................ 39
Figure 5-9: Transport Channel Interface ....................................................................................... 40
Figure 5-10: ITU-R BT.656 NTSC/PAL Decoder Interface ......................................................... 41
Figure 5-11: NTSC/PAL Encoder Interface .................................................................................. 41
Figure 5-12: CRT .......................................................................................................................... 42
Figure 5-13: I2C Interface ............................................................................................................. 42
Figure 5-14: ROM Connections .................................................................................................... 43
Figure 6-1: SDRAM Timing Measurement Conditions ................................................................ 49
Figure 6-2: PCI Output Timing Measurement Conditions ............................................................ 50
Figure 6-3: PCI Input Timing Measurement Conditions .............................................................. 50
Figure 6-4: I2S Data Format .......................................................................................................... 52
Figure 6-5: I2S Output Timing Measurement Conditions ............................................................. 53
Figure 6-6: I2S Input Timing Measurement - Slave Mode ........................................................... 53
Figure 6-7: I2S Input Timing Measurement - Master Mode ......................................................... 54
Figure 6-8: Internal Serial Clock Generation for I2S Master Mode .............................................. 55
Figure 6-9: TCI Timing Measurement Conditions ....................................................................... 55
Figure 6-10: ITU-R BT.601/656 Input Timing Measurement Conditions .................................... 56
Figure 6-11: ITU-R BT.601/656 Output Timing Measurement Conditions ................................. 57
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MAP-CA DSP Datasheet
June 20, 2001
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11 Page | ||
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| PDF Descargar | [ Datasheet MAP-CA.PDF ] | |
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