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PDF TC74ACT273FW Data sheet ( Hoja de datos )
| Número de pieza | TC74ACT273FW | |
| Descripción | Octal D-Type Flip Flop with Clear | |
| Fabricantes | Toshiba Semiconductor | |
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TC74ACT273P/F/FW
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74ACT273P,TC74ACT273F,TC74ACT273FW
Octal D-Type Flip Flop with Clear
The TC74ACT273 is an advanced high speed CMOS OCTAL
D-TYPE FLIP FLOP fabricated with silicon gate and
double-layer metal wiring C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
This device may be used as a level converter for interfacing
TTL or NMOS to High Speed CMOS. The inputs are compatible
with TTL, NMOS and CMOS output voltage levels.
Information signals applied to D inputs are transferred to the
Q outputs on the positive going edge of the clock pulse.
When the CLR input is held “L”, the Q outputs are at a low
logic level independent of the other inputs.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: fmax = 170 MHz (typ.) at VCC = 5 V
• Low power dissipation: ICC = 8 μA (max) at Ta = 25°C
• Compatible with TTL outputs: VIL = 0.8 V (max)
VIH = 2.0 V (min)
• Symmetrical output impedance: |IOH| = IOL = 24 mA (min)
Capability of driving 50 Ω
transmission lines.
• Balanced propagation delays: tpLH ∼− tpHL
• Pin and function compatible with 74F273
Pin Assignment
Note: xxxFW (JEDEC SOP) is not available in
Japan.
TC74ACT273P
TC74ACT273F
TC74ACT273FW
Weight
DIP20-P-300-2.54A
SOP20-P-300-1.27A
SOP20-P-300-1.27
SOL20-P-300-1.27
: 1.30 g (typ.)
: 0.22 g (typ.)
: 0.22 g (typ.)
: 0.46 g (typ.)
1 2006-06-01
1 page  
TC74ACT273P/F/FW
AC Characteristics (CL = 50 pF, RL = 500 Ω, input: tr = tf = 3 ns)
Characteristics
Propagation delay
time
(CK-Q)
Propagation delay
time
( CLR -Q)
Maximum clock
frequency
Input capacitance
Power dissipation
capacitance
Symbol
tpLH
tpHL
tpHL
fmax
CIN
CPD
(Note)
Test Condition
VCC (V)
Ta = 25°C
Min Typ. Max
⎯
5.0 ± 0.5 ⎯
6.6 10.5
⎯
⎯
⎯
⎯
5.0 ± 0.5 ⎯
7.4 10.8
5.0 ± 0.5 80 150 ⎯
⎯ 5 10
⎯ 34 ⎯
Ta = −40 to
85°C
Min Max
Unit
1.0 12.0 ns
1.0 12.3 ns
80 ⎯ MHz
⎯ 10 pF
⎯ ⎯ pF
Note:
CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD･VCC･fIN + ICC/8 (per F/F)
And the total CPD when n pcs. of Flip Flop operate can be gained by the following equation.
CPD (total) = 23 + 11･n
5 2006-06-01
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet TC74ACT273FW.PDF ] | |
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