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PDF TC74ACT175F Data sheet ( Hoja de datos )

Número de pieza TC74ACT175F
Descripción Quad D-Type Flip Flop with Clear
Fabricantes Toshiba Semiconductor 
Logotipo Toshiba Semiconductor Logotipo



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TC74ACT175P/F/FN
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74ACT175P,TC74ACT175F,TC74ACT175FN
Quad D-Type Flip Flop with Clear
The TC74ACT175 is an advanced high speed CMOS QUAD
D-TYPE FLIP FLOP fabricated with silicon gate and
double-layer metal wiring C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
This device may be used as a level converter for interfacing
TTL or NMOS to High Speed CMOS. The inputs are compatible
with TTL, NMOS and CMOS output voltage levels.
These four flip-flops are controlled by a clock input (CK) and a
clear input ( CLR ).
The information data applied to the D inputs (D1 thru D4) are
transferred to the outputs (Q1 thru Q4 and Q1 thru Q4 ) on the
positive-going edge of the clock pulse.
Reset function is accomplished when the clear input is taken
low, and all Q outputs are kept in low level regardless of other
input conditions.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
High speed: fmax = 160 MHz (typ.) at VCC = 5 V
Low power dissipation: ICC = 8 μA (max) at Ta = 25°C
Compatible with TTL outputs: VIL = 0.8 V (max)
VIH = 2.0 V (min)
Symmetrical output impedance: |IOH| = IOL = 24 mA (min)
Capability of driving 50 Ω
transmission lines.
Balanced propagation delays: tpLH ∼− tpHL
Pin and function compatible with 74F175
Pin Assignment
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74ACT175P
TC74ACT175F
TC74ACT175FN
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
SOL16-P-150-1.27
: 1.00 g (typ.)
: 0.18 g (typ.)
: 0.13 g (typ.)
Downloaded from Elcodis.com electronic components distributor
1
2007-10-01

1 page




TC74ACT175F pdf
TC74ACT175P/F/FN
AC Characteristics (CL = 50 pF, RL = 500 Ω, input: tr = tf = 3 ns)
Characteristics
Propagation delay
time
(CK-Q, Q )
Propagation delay
time
( CLR -Q, Q )
Maximum clock
frequency
Input capacitance
Power dissipation
capacitance
Symbol
tpLH
tpHL
tpLH
tpHL
fmax
CIN
CPD
(Note)
Test Condition
VCC (V)
Ta = 25°C
Min Typ. Max
5.0 ± 0.5
6.9 11.0
5.0 ± 0.5
6.5 10.4
5.0 ± 0.5 80 145
5 10
46
Ta = −40 to
85°C
Min Max
Unit
1.0 12.5 ns
1.0 11.8 ns
80 MHz
10 pF
⎯ ⎯ pF
Note:
CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPDVCCfIN + ICC/4 (per F/F)
And the total CPD when n pcs of Flip Flop operate can be gained by the following equation.
CPD (total) = 25 + 21n
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