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PDF TC74AC257FN Data sheet ( Hoja de datos )

Número de pieza TC74AC257FN
Descripción 2-Channel Multiplexer
Fabricantes Toshiba Semiconductor 
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TC74AC257,258P/F/FN
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74AC257P,TC74AC257F,TC74AC257FN
TC74AC258P,TC74AC258F,TC74AC258FN
TC74AC257P/F/FN 2-Channel Multiplexer (3-state)
TC74AC258P/F/FN 2-Channel Multiplexer (3-state,
inverting)
The TC74AC257 and TC74AC258 are advanced high speed
CMOS MULTIPLEXERs fabricated with silicon gate and
double-layer metal wiring C2MOS technology.
They achieve the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
Each is composed of four independent 2-channel multiplexers
with common SELECT and OUTPUT ENABLE ( OE ).
The TC74AC257 is a non-inverting multiplexer, while the
TC74AC258 is an inverting.
If OE is set low, the outputs are held in a high-impedance
state. When SELECT is set low, “A” data inputs are enabled.
Conversely, when SELECT is high, “B” data inputs are
enabled.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74AC257P, TC74AC258P
TC74AC257F, TC74AC258F
Features
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High speed: tpd = 3.6 ns (typ.) at VCC = 5 V
Low power dissipation: ICC = 8 µA (max) at Ta = 25°C
High noise immunity: VNIH = VNIL = 28% VCC (min)
Symmetrical output impedance: |IOH| = IOL = 24 mA (min)
Capability of driving 50
transmission lines.
Balanced propagation delays: tpLH ∼− tpHL
Wide operating voltage range: VCC (opr) = 2~5.5 V
Pin and function compatible with 74F257/258
TC74AC257FN, TC74AC258FN
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Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
SOP16-P-300-1.27
SOL16-P-150-1.27
: 1.00 g (typ.)
: 0.18 g (typ.)
: 0.18 g (typ.)
: 0.13 g (typ.)
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TC74AC257FN pdf
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TC74AC257,258P/F/FN
AC Characteristics (CL = 50 pF, RL = 500 , input: tr = tf = 3 ns)
Characteristics
Propagation delay
time
(A, B-Y, Y )
Symbol
tpLH
tpHL
Test Condition
VCC (V)
3.3 ± 0.3
5.0 ± 0.5
Ta = 25°C
Min Typ. Max
7.0 14.3
4.7 7.5
Propagation delay
time
(SELECT-Y, Y )
tpLH
tpHL
3.3 ± 0.3
8.6 17.2
5.0 ± 0.5 5.5 9.1
Output enable time
Output disable time
Input capacitance
Output capacitance
Power dissipation
capacitance
tpZL
tpHZ
tpLZ
tpHZ
CIN
COUT
CPD
(Note)
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
7.3 14.0
5.0 7.9
5.6 9.6
5.1 7.9
5 10
10
28
Ta = −40~85°C
Min Max
1.0 16.3
1.0 8.5
1.0 19.6
1.0 10.4
1.0 16.0
1.0 9.0
1.0 11.0
1.0 9.0
10
⎯⎯
⎯⎯
Unit
ns
ns
ns
ns
pF
pF
pF
Note:
CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPDVCCfIN + ICC/4 (per bit)
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