PDF TC74AC112F Data sheet ( Hoja de datos )

Número de pieza	TC74AC112F
Descripción	DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
Fabricantes	Toshiba Semiconductor
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No Preview Available ! www.DataSheet4U.com TC74AC112P/F/FN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC112P,TC74AC112F,TC74AC112FN Dual J-K Flip Flop with Preset and Clear The TC74AC112 is an advanced high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. In accordance with the logic level given J and K input this device changes state on negative going transition of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low logic level on the corresponding input. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Note: xxxFN (JEDEC SOP) is not available in Japan. TC74AC112P TC74AC112F Features • High speed: fmax = 170 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 µA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Symmetrical output impedance: \|IOH\| = IOL = 24 mA (min) Capability of driving 50 Ω transmissioDnalitnaeSsh. eet4U.com • Balanced propagation delays: tpLH ∼− tpHL • Wide operating voltage range: VCC (opr) = 2 to 5.5 V • Pin and function compatible with 74F112 Pin Assignment TC74AC112FN DataShee DataSheet4U.com DataSheet4 U .com Weight DIP16-P-300-2.54A SOP16-P-300-1.27A SOP16-P-300-1.27 SOL16-P-150-1.27 : 1.00 g (typ.) : 0.18 g (typ.) : 0.18 g (typ.) : 0.13 g (typ.) 1 2006-02-01 1 page www.DataSheet4U.com Timing Requirements (input: tr = tf = 3 ns) Characteristics Symbol Minimum pulse width ( CK ) Minimum pulse width ( CLR , PR ) Minimum set-up time Minimum hold time Minimum removal time ( CLR , PR ) tW (L) tW (H) tW (L) ts th trem TC74AC112P/F/FN Test Condition ⎯ ⎯ ⎯ ⎯ ⎯ VCC (V) 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 Ta = 25°C Limit Ta = −40 to 85°C Limit 7.5 7.5 5.0 5.0 7.0 7.0 5.0 5.0 11.0 11.0 6.0 6.0 0.0 0.0 0.0 0.0 3.0 3.0 2.0 2.0 Unit ns ns ns ns ns et4U.com AC Characteristics (CL = 50 pF, RL = 500 Ω, input: tr = tf = 3 ns) Characteristics Propagation delay time ( CK -Q, Q ) Propagation delay time ( CLR , PR -Q, Q ) Maximum clock frequency Input capacitance Power dissipation capacitance Symbol tpLH tpHL tpLH tpHL fmax CIN CPD (Note) Test Condition VCC (V) 3.3 ± 0.3 ⎯ 5.0 ± 0.5 Ta = 25°C Min Typ. Max ⎯ 9.1 15.5 ⎯ 6.5 9.4 3.3 ± 0.3 ⎯ 5.0 ± 0.5 DataSheet4U.com 3.3 ± 0.3 ⎯ 5.0 ± 0.5 ⎯ ⎯ ⎯ 45 80 ⎯ ⎯⎯ 8.6 14.6 5.8 8.3 90 ⎯ 150 ⎯ 5 10 85 ⎯ Ta = −40 to 85°C Min Max 1.0 17.8 1.0 10.8 Unit ns 1.0 16.8 1.0 9.6 ns 45 ⎯ MHz 80 ⎯ ⎯ 10 pF ⎯ ⎯ pF Note: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD･VCC･fIN + ICC/2 (per F/F) DataShee DataSheet4U.com DataSheet4 U .com 5 2006-02-01 5 Page

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Número de pieza	Descripción	Fabricantes
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TC74AC112P	DUAL J-K FLIP FLOP WITH PRESET AND CLEAR	Toshiba Semiconductor

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