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PDF VT82C580VPX Data sheet ( Hoja de datos )
| Número de pieza | VT82C580VPX | |
| Descripción | OCI North Bridge | |
| Fabricantes | VIA | |
| Logotipo |  |
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LIST OF FIGURES
VT82C580VPX
FIGURE 1. APOLLO VPX SYSTEM BLOCK DIAGRAM......................................................................................................... 3
FIGURE 2. VT82C585VPX PIN DIAGRAM (TOP VIEW) ......................................................................................................... 5
FIGURE 3. VT82C585VPX PIN LIST (ALPHABETICAL ORDER) ......................................................................................... 6
FIGURE 4. VT82C587VP PIN DIAGRAM (TOP VIEW) .......................................................................................................... 11
FIGURE 5. VT82C587VP PIN LIST (ALPHABETICAL ORDER) .......................................................................................... 12
FIGURE 6. DRAM READ PIPE LINE EDO 5-2-2-2, 3-2-2-2 .................................................................................................... 30
FIGURE 7. POST WRITE 3111,DRAM EDO 2222 .................................................................................................................... 31
FIGURE 8. SDRAM READ CYCLE (BANK INTERLEAVE, CAS LATENCY=3) ................................................................ 32
FIGURE 9. SDRAM WRITE CYCLE (BANK INTERLEAVE) ................................................................................................ 33
FIGURE 10. CPU READ HIT SYNCHRONOUS SRAM 3111 .................................................................................................. 34
FIGURE 11. CPU WRITE HIT SYNCHRONOUS SRAM 3111................................................................................................ 35
FIGURE 12. CPU READ MISS FILL SYNCHRONOUS SRAM .............................................................................................. 36
FIGURE 13. CPU READ MISS DIRTY L2 WRITE BACK FILL............................................................................................. 37
FIGURE 14. CPU READ PCI SLAVE.......................................................................................................................................... 38
FIGURE 15. CPU WRITE PCI SLAVE WRITE BUFFER ON FAST BACK TO BACK ...................................................... 39
FIGURE 16. PCI MASTER READ HIT DRAM.......................................................................................................................... 40
FIGURE 17. PCI MASTER READ L1 SNOOP TO DRAM....................................................................................................... 41
FIGURE 18. PCI MASTER READ HIT L2 ................................................................................................................................. 42
FIGURE 19. PCI MASTER READ L1 SNOOP TO L2............................................................................................................... 43
FIGURE 20. PCI MASTER WRITE DRAM ............................................................................................................................... 44
FIGURE 21. PCI MASTER WRITE HIT L1 SNOOP TO DRAM ............................................................................................ 45
FIGURE 22. PCI MASTER WRITE HIT L2 ............................................................................................................................... 46
et4U.com FIGURE
FIGURE
23.
24.
PCI MASTER WRITE HIT
PCI MASTER WRITE HIT
L2, L1 HITM ............................................................................................................
L2 & DIRTY .............................................................................................................
47
48
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FIGURE 25. MECHANICAL SPECIFICATIONS -D2a0t8a-SPhINeePt4LUA.ScToImC FLAT PACKAGE.................................................. 49
FIGURE 26. MECHANICAL SPECIFICATIONS - 100-PIN PLASTIC FLAT PACKAGE.................................................. 50
DataSheet4U.com
Preliminary Revision 0.1 January 9, 1997
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List of Figures
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PINOUTS
VT82C585VPX Pinouts
Figure 2. VT82C585VPX Pin Diagram (Top View)
VT82C580VPX
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REQ2#
GNT1#
REQ1#
GNT0#
REQ0#
SCASC#
CPURSTO
GND
VDD
CPURSTI
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
GND
CBE3#
AD23
AD22
AD21
AD20
AD19
AD18
GND
VDD-PCI
AD17
AD16
CBE2#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
LOCK#
PAR
SERR#
CBE1#
AD15
AD14
AD13
GND
VDD-PCI
AD12
AD11
AD10
AD9
AD8
CBE0#
AD7
157 I
158 O
159 I
160 O
161 I
162 O
163 O
164
165
166 I
167 IO
168 IO
169 IO
170 IO
171 IO
172 IO
173 IO
174 IO
175
176 IO
177 IO
178 IO
179 IO
180 IO
181 IO
182 IO
183
184
185 IO
186 IO
187 IO
188 IO
189 IO
190 IO
191 IO
192 IO
193 IO
194 IO
195 IO
196 IO
197 IO
198 IO
199 IO
200
201
202 IO
203 IO
204 IO
205 IO
206 IO
207 IO
208 IO
(DQM7#) O 104
(MA13) O 103
O 102
(CS1#) O 101
(CS0#) O 100
(CS3#) O 99
(CS2#) O 98
97
96
(SWEC#) O 95
(CE1#) O 94
(SCASB#) O 93
(SCASA#) O 92
(BWE#) O 91
(GWE#) O 90
97&93;DataSheet4U.com
O 89
(DB32) IO 88
IO 87
IO 86
IO 85
84
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83
IO 82
IO 81
IO 80
IO 79
34)3
IO 78
IO 77
(SWEB#) O 76
(SWEA#) O 75
(SRASB#) O 74
(SRASA#) O 73
O 72
(CADS#) O 71
(CADV#) O 70
I 69
I 68
I 67
I 66
O 65
O 64
O 63
Note: Pin names in parentheses (...) indicate alternate function
O 62
61
60
I 59
I 58
O 57
O 56
I 55
I 54
I 53
CAS7#
RAS5#
RAS4#
RAS1#
RAS0#
RAS3#
RAS2#
VDD-DRAM
GND
WE#
CALE
CWE3#
CWE2#
CWE1#
CWE0#
TWE#
TA9
TA8
TA3
TA4
VDD-CPU
GND
TA5
TA6
TA7
TA2
TA1
TA0
CWE7#
CWE6#
CWE5#
CWE4#
COE#
A3SEL
A4SEL
W/R#
HITM#
D/C#
ADS#
EADS#
BOFF#
NA#
BRDY#
VDD-CPU
GND
HCLK
SMIACT#
AHOLD
KEN#/INV
CACHE#
M/IO#
HLOCK#
DataShee
DataSheet4U.com
Preliminary Revision 0.1 January 9, 1997
DataSheet4 U .com
-5-
VT82C585VPX Pinouts
11 Page | ||
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