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PDF PEB3035 Data sheet ( Hoja de datos )

Número de pieza PEB3035
Descripción Primary Rate Interface Signaling and Maintence Controller
Fabricantes Siemens 
Logotipo Siemens Logotipo



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Primary Rate Interface Signaling
and Maintenance Controller
(PRISM)
Preliminary Data
PEB 3035
CMOS IC
Features
Serial Interface
q Two independent signaling/maintenance channels
programmable in a
– serial mode
– strobe mode
– time-slot assignment mode
q Programmable bit inversion
q Zero bit stuffing
q Programmable idle code (Flags, all ones)
q Continuous transmission of up to 32-bytes data
q Data rate up to 4 Mbit/s
Protocol Support
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q Support of the ESF-DL protocol according to T1.403-1989
or according to AT & T TR 54016
q Support of HDLC protocol
q Transparent mode for totally transparent data transmission
and reception
P-LCC-28-R
P-DIP-28
µP Interface
q 8-bit multiplexed µP-interface
(SIEMENS/Intel type of µP interface)
q 64-byte FIFO per channel and direction
q Efficient transfer of data blocks from/to system memory by interrupt request
General
q P-DIP-28 or P-LCC-28-R package
q Advanced CMOS technology
q Low power consumption
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Type
PEB 3035-N
PEB 3035-P
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Semiconductor Group
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Version
V1.1
V1.1
Ordering Code
Q67100-H6242
Q67100-H6243
219
Package
P-LCC-28-R (SMD)
P-DIP-28
01.94

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PEB 3035
Pin Definitions and Functions (cont’d)
Pin No.
16
14
15
19
18
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Symbol
ALE
VSS
INT
TxCLKA
TxCLKB
Input (I)
Output (O)
Function
I Address Latch Enable
A high on this line indicates an address on the
external address/data bus.
Ground (0 V)
OD Interrupt Request
The signal is activated when the PRISM requests an
interrupt (active low). INT is an open drain output.
This pin must be connected to pull-up resistor.
I Transmit Clock, (channel A/channel B)
I/O These pins can be programmed in several different
modes of operation. T×CLK may supply
- the transmit clock for the respective channel (clock
mode 0)
- a transmit strobe signal (clock mode 1)
DataS- haeferta4mU.ecosmync. signal (T×CLKA, clock mode 2)
Programmed as output, the T×CLKB pin supplies a
tristate control signal, indicating the programmed
transmit time slot (clock mode 2).
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21 RxCLKA I
20 RxCLKB I
22 VDD I
Receive Clock, (channel A/channel B)
These pins can be programmed in several different
operation modes. In each channel the R×CLK pins
may supply
q the receive clock (clock mode 0)
q the receive and transmit clock (clock mode 1, 2).
Power
+ 5 V power supply
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PEB 3035
Figure 3
Yellow Alarm Detection, Example
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Transmit Direction
Operating in BOM mode, Clock Configuration Register 1 (CCR1) may be programmed to BOM
interframe timefill mode where one of four idle codes may be selected (CCR1: ITM, IT1, IT0 see
Register Definitions). Therefore yellow alarm can be issued by programming ITM = 1, IT1 = 0,
IT2 = 0.
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A BOM frame may be initiated by the CPU either as a transparent frame or a cyclic transmission
frame.
In a special transparent transmission mode (MODE: TXM, see Register Definitions) the PRISM
generates a sync byte (FFH) in front of every data byte. Therefore only data bytes have to be
entered into XFIFO, the requested interrupt reaction time is doubled. This mode may also be used
with a cyclic transmission frame.
Note: A transparent frame may also be transmitted with ‘idle’ or ‘flags’ as interframe timefill.
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Operating Modes
The HDLC controller of each channel can be programmed to operate in various modes, which are
different in the treatment of the frames in receive direction. Thus, the receive data flow and the
address recognition features can be effected in a very flexible way, which satisfies a whole variety
of requirements.
There are 6 different operating modes which can be set via the MODE register.
2-Byte Address Comparison
The high address byte is compared with three individually programmable values in RAH1, RAH2
and RAH3 registers. Bit 1 of the high byte address is excluded from the address comparison of
RAH1 (7 bit) and is included with RAH2 and RAH3 (8 bit). The result of the address comparison is
stored in the Receive Status Register (RSTA:HAD1,0, see Register Definitions).
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