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PDF K4S561632H Data sheet ( Hoja de datos )

Número de pieza K4S561632H
Descripción 256Mb H-Die SDRAM
Fabricantes Samsung Electronics 
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No Preview Available ! K4S561632H Hoja de datos, Descripción, Manual

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SDRAM 256Mb H-die (x4, x8, x16)
CMOS SDRAM
256Mb H-die SDRAM Specification
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
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* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.0 October 2005
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K4S561632H pdf
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SDRAM 256Mb H-die (x4, x8, x16)
FUNCTIONAL BLOCK DIAGRAM
CMOS SDRAM
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Data Input Register
Bank Select
CLK
ADD
16M x 4 / 8M x 8 / 4M x 16
16M x 4 / 8M x 8 / 4M x 16
16M x 4 / 8M x 8 / 4M x 16
16M x 4 / 8M x 8 / 4M x 16
Column Decoder
LCKE
LRAS
LCBR
Latency & Burst Length
LWE
Programming Register
LCAS
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LWCBR
Timing Register
LWE
LDQM
DQi
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
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K4S561632H arduino
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SDRAM 256Mb H-die (x4, x8, x16)
CMOS SDRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
CLK cycle time
CLK to valid
output delay
Output data
hold time
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output in Hi-Z
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
Symbol
tCC
tSAC
tOH
tCH
tCL
tSS
tSH
tSLZ
tSHZ
60
Min Max
6
1000
-
5
-
2.5
-
2.5
2.5
1.5
1
1
5
-
75
Min Max
Unit
Note
7.5
1000
ns
10
1
5.4
ns 1,2
6
3
ns 2
3
2.5 ns 3
2.5 ns 3
1.5 ns 3
0.8 ns 3
1 ns 2
5.4
ns
6
Notes : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
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DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Output rise time
Output fall time
Output rise time
Output fall time
Symbol
trh
tfh
trh
tfh
Condition
Measure in linear
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
Min
1.37
1.30
2.8
2.0
Typ
3.9
2.9
Notes : 1. Rise time specification based on 0pF + 50 to VSS, use these values to design to.
2. Fall time specification based on 0pF + 50 to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS.
Max
4.37
3.8
5.6
5.0
Unit
Volts/ns
Volts/ns
Volts/ns
Volts/ns
Notes
3
3
1,2
1,2
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Rev. 1.0 October 2005

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