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PDF TC9256APG Data sheet ( Hoja de datos )

Número de pieza TC9256APG
Descripción (TC9256Axx / TC9257Axx) PLL for DTS
Fabricantes Toshiba 
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TC9256, 57APG/AFG
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9256APG, TC9256AFG, TC9257APG,
TC9257AFG
PLL for DTS
The TC9256APG, TC9256AFG, TC9257APG and TC9257AFG
are phase-locked loop (PLL) LSIs for digital tuning systems (DTS)
with built-in two-modulus prescalers.
All functions are controlled through three serial bus lines.
These LSIs are used to configure high-performance digital
tuning systems.
TC9256APG
Features
Suitable for use in digital tuning systems in high-fi tuners and
car stereos.
Built-in prescalers operate at an input frequency ranging from
30 to 150 MHz during FMIN input (with two-modulus
prescaler) and at 0.5 to 40 MHz during AMIN input (with
two-modulus prescaler or direct dividing)
16-bit programmable counter, dual parallel output phase
comparator, crystal oscillator and reference counter
3.6 MHz, 4.5 MHz, 7.2 MHz or 10.8 MHz crystal oscillators can
be used.
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15 possible reference frequencies (when using 4.5 MHz
crystal):ref. = 0.5 k, 1 k, 2.5 k, 3 k, 3.125 k, 3.90625 k, 5 k, 6.25
k, 7.8125 k, 9 k, 10 k, 12.5 k, 25 k, 50 k and 100 kHz.
Built-in 20-bit general-purpose counter for such uses as
measuring intermediate frequencies (IFIN1 and IFIN2) and
low-frequency pilot signal cycles (SCIN). (No cycle
measurement function is available on the TC9256APG and
TC9256AFG.)
High-precision (±0.55 to ±7.15 µs) PLL phase error detection
Numerous general-purpose I/O pins for such uses as
peripheral circuit control
Four N-channel open-drain output ports (OFF withstanding
voltage: 12 V) for such uses as control signal output.
(TC9256APG and TC9256AFG have only three ports.)
Standby mode function (turns off FM, AM and IF amps) to
save current consumption
All functions controlled through three serial bus lines
CMOS structure with operating power supply range of VDD =
5.0 ± 0.5 V.
16-pin DIP (TC9256APG), 20-pin DIP (TC9257APG), 16-pin
SOP (TC9256AFG), 20-pin SOP (TC9257AFG) packages
TC9257APG
TC9256AFG
TC9257AFG
Weight
P-DIP16-300-2.54A: 1.0 g (typ.)
P-DIP20-300-2.54A: 1.24 g (typ.)
P-SOP16-300-1.27A: 0.16 g (typ.)
P-SOP20-300-1.27A: 0.48 g (typ.)
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TC9256APG pdf
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TC9256, 57APG/AFG
Functions and Operation
Serial I/O Ports
As the block diagram shows, the functions of the TC9256APG, TC9256AFG, TC9257APG and TC9257AFG are
controlled by setting data in the 48 bits contained in each of the two sets of 24-bit registers. Each bit of data in
these registers is transferred through the serial ports between the controller and the DATA, CLOCK and
PERIOD pins. Each serial transfer consists of a total of 32 bits, with 8 address bits and 24 data bits.
Since all functions are controlled in units of registers, the explanation here focuses on the 8-bit addresses and
functions of each register.
These registers consist of 24 bits and are selected by an 8-bit address.
A list of the address assignments for each register is given below under Register Assignments.
et4U.com
Register
Input Register 1
Input Register 2
Output Register 1
Output Register 2
Address
D0H
D2H
D1H
D3H
24-Bit Composition
PLL divisor setting
Reference frequency setting
PLL input and mode setting
Crystal oscillator selection
General-purpose counter control
(Including lock-detection bit control)
I/O port and general-purpose counter switching bits
I/O-5/CLK pin switching bit
(DO2/OT-4 pin switching bit for TC9256APG and
TC9256AFG)
DO pin control
TEST bit
I/O port control
(Also used as general-purpose counter input-selection
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Output data
General-purpose counter numeric data
Not used
Lock detection data
I/O port control data
Output data
Input data (undefined during output port selection)
Not used
No. of Bits
Total
16
4
2
2
24
4
3
1
1
1
5
Total
Total
Total
9
24
22
2
24
5
5
4
5
5
24
On the falling edge of the PERIOD signal, the input data is latched in register 1 or register 2 and the function
is performed.
On the ninth falling edge of the CLOCK signal, the output data is latched in parallel in the output registers.
The data are subsequently output serially from the data pin.
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TC9256APG arduino
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TC9256, 57APG/AFG
2. Prescaler and Programmable Counter Circuit Configuration
(1) Pulse-swallow mode circuit configuration
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Figure 3
This circuit consists of a two-modulus prescaler, a 4-bit swallow counter and a 12-bit programmable
counter. During FMIN (FMH mode), a 1/2 prescaler is added to the preceding step.
(2) Circuit configuration for the direct dividing method
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Figure 4
In the direct dividing mode, the prescaler section is bypassed and the 12-bit programmable counter
is used.
Note: Both FMIN and AMIN have built-in amps. Connecting a capacitor permits low-amplitude
operation.
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