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Número de pieza | THC63LVDM63R | |
Descripción | (THC63LVDM63R / THC63LVDM83R) Reduced Swing LVDS 24-Bit / 18-Bit Color Host LCD Panel Interface | |
Fabricantes | THine Electronics | |
Logotipo | ||
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THC63LVDM83R/THC63LVDM63R_Rev2.0
THC63LVDM83R/THC63LVDM63R
REDUCED SWING LVDS 24Bit/18Bit COLOR HOST-LCD PANEL INTERFACE
General Description
Features
The THC63LVDM83R transmitter converts 28bits of
CMOS/TTL data into LVDS (Low Voltage Differential
Signaling) data stream. A phase-locked transmit clock
is transmitted in parallel with the data streams over a
fifth LVDS link. At a transmit clock frequency of
85MHz, 28bits of RGB data and 4bits of LCD timing
and control data (HSYNC, VSYNC, CNTL1, CNTL2)
• 28:4 Data channel compression at up to
298 Megabytes per sec throughput
• Wide dot clock range: 20-85MHz suited for VGA,
SVGA, XGA and SXGA
• Narrow bus (10 lines or 8 lines) reduces cable size
• Support Reduced swing LVDS for Low EMI
are transmitted at a rate of 595Mbps per LVDS channel.
Also available is THC63LVDM63R that converts 21bits
of CMOS/TTL data into LVDS(Low Voltage Differen-
tial Signaling) data stream. Both transmitters can be
programmed reduced swing LVDS through a dedicated
pin for low power consumption and EMI.
• 200mV swing LVDS/350mV swing LVDS
selectable
• Support Spread Spectrum Clock Generator
• On chip Input Jitter Filtering
• PLL requires No external components
• Single 3.3V supply with 125mW(TYP)
• Power-Down Mode
• Low profile 56 or 48 Lead TSSOP Package
• Clock Edge Programmable
• Improved Replacement for the National DS90C383
or DS90C363
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Block Diagram
DataShee
CMOS/TTL
INPUTS
TA0-6
TB0-6
7
7
TC0-6 7
TD0-6 7
TRANSMITTER
CLOCK IN
(20 to 85MHz)
R/F
/PDWN
RS
THC63LVDM83R
PLL
DATA
(LVDS)
TA +/-
TB +/-
TC +/-
CMOS/TTL
INPUTS
TA0-6 7
TB0-6 7
TC0-6 7
THC63LVDM63R
DATA
(LVDS)
TA +/-
TB +/-
TC +/-
TD +/-
(140-595Mbit/On Each
(140-595Mbit/On Each
LVDS Channel)
LVDS Channel)
TCLK +/-
TRANSMITTER
CLOCK IN
PLL
TCLK +/-
CLOCK
(LVDS)
(20 to 85MHz)
R/F
CLOCK
(LVDS)
20-85MHz
/PDWN
20-85MHz
RS
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THC63LVDM83R /THC63LVDM63R_Rev2.0
LVDS Transmitter DC Specifications
VCC = 3.0V ~ 3.6V, Ta = -10 °C ~ +70 °C
Symbol
Parameter
Conditions
Min. Typ. Max. Units
VOD Differential Output Voltage
RL=100Ω
Normal
swing
RS=VCC
Reduced
swing
RS=GND
250 350 450 mV
100 200 300 mV
∆VOD
Change in VOD between
complementary output states
35 mV
VOC Common Mode Voltage
RL=100Ω
1.125 1.25 1.375 V
∆VOC
Change in VOC between
complementary output states
35 mV
IOS Output Short Circuit Current VOUT=0V, RL=100Ω
-24 mA
/PDWN=0V,
IOZ Output TRI-STATE Current VOUT=0V to VCC
±10 µA
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THC63LVDM83R Supply Current
VCC = 3.0V ~ 3.6V, Ta = -10 °C ~ +70 °C
Symbol
Parameter
Condition(*)
Typ. Max. Units
ITCCG
Transmitter Supply
Current
RL=100Ω,CL=5pF
f=65MHz
VCC=D3a.3taVS, RheSe=tV4CUC.com f=85MHz
16 Gray Scale Pattern
RL=100Ω,CL=5pF
f=65MHz
36 46 mA
39 49 mA
31 41 mA
VCC=3.3V, RS=GND
16 Gray Scale Pattern
f=85MHz
34 44 mA
RL=100Ω,CL=5pF
f=65MHz
38 48 mA
ITCCW
Transmitter Supply
Current
VCC=3.3V, RS=VCC
Worst Cace Pattern
RL=100Ω,CL=5pF
f=85MHz
f=65MHz
41 51 mA
33 43 mA
VCC=3.3V, RS=GND
Worst Cace Pattern
f=85MHz
36 46 mA
ITCCS
Transmitter Power Down
Supply Current
/PDWN = L
10 µA
.
DataShee
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THC63LVDM83R /THC63LVDM63R_Rev2.0
Package
56 Lead Molded Thin Shrink Small Outline Package, JEDEC
14.0 ± 0.1
56
Unit : millimeters
29
8.1 ± 0.1
4.05
1
0.50 TYP
0.20 TYP
6.1 ± 0.1
28
(1.0)
1.2 MAX
0.10 ± 0.05
et4U.com
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48 Lead Molded Thin Shrink Small Outline Package, JEDEC
12.5 ± 0.1
48 25
Unit : millimeters
8.1 ± 0.1
4.05
1
0.50 TYP
6.1 ± 0.1
0.20 TYP
24
(1.0)
1.2 MAX
0.10 ± 0.05
DataShee
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11 Page |
Páginas | Total 12 Páginas | |
PDF Descargar | [ Datasheet THC63LVDM63R.PDF ] |
Número de pieza | Descripción | Fabricantes |
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THC63LVDM63R | (THC63LVDM63R / THC63LVDM83R) Reduced Swing LVDS 24-Bit / 18-Bit Color Host LCD Panel Interface | THine Electronics |
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