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PDF 97C2051 Data sheet ( Hoja de datos )

Número de pieza 97C2051
Descripción GMS97C2051
Fabricantes Hynix Semiconductor 
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8-Bit CMOS Microcontorller
GMS97C2051/L2051
Features
 Compatible with MCS-51TM Products
 2 Kbytes of programmable EPROM
 4.25V to 5.5V Operating Range (GMS97C2051)
2.70V to 3.6V Operating Range (GMS97L2051)
 Version for 12MHz / 24 MHz Operating frequency (GMS97C2051)
Only 12MHz Operating frequency (GMS97L2051)
 Two-Level Program Memory Lock with encryption array
 128 bytes SRAM
 15 Programmable I/O Lines
 Two 16-Bit Timer/Counters
 Programmable serial USART
 Five Interrupt Sources
 Direct LED Drive Outputs
 On-Chip Analog Comparator
 Low Power Idle and Power Down Modes
Description
The GMS97C2051/L2051 is a high-performance CMOS 8-bit microcontroller with 2Kbytes of programmable
EPROM. The device is compatible with the industry standard MCS-51TM instruction set and pinout. The HYUN-
DAI MicroElectronics GMS97C2051/L2051 is a powerful microcontroller which provides a highly flexible and
cost effective solution to many embedded control applications. The GMS97C2051/L2051 provides the following
standard features: 2Kbytes of EPROM, 128 bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five vector
two-level interrupt architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator and
clock circuitry. In addition, the GMS97C2051/L2051 supports two software selectable power saving modes. The
Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue
functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip
functions until the next hardware reset.
Pin Configuration
PDIP/SOP
RST
(RXD) P3.0
(TXD) P3.1
XTAL2
XTAL1
( INT0 )P3.2
( INT1) P3.3
(T0) P3.4
(T1) P3.5
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 P1.7
18 P1.6
17 P1.5
16 P1.4
15 P1.3
14 P1.2
13 P1.1 (AIN1)
12 P1.0 (AIN0)
11 P3.7
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97C2051 pdf
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8-Bit CMOS Microcontorller
GMS97C2051/L2051
Table 2. Bit Assignment of SFRs
Address Register
81H SP
82H DPL
83H DPH
87H PCON
88H TCON
89H TMOD
8AH TL0
8BH TL1
8CH TH0
8DH TH1
90H P1
98H SCON
99H SBUF
A8H IE
B0H P3
B8H IP
D0H PSW
E0H ACC
F0H B
Bit7
SMOD
TF1
GATE
SM0
EA
-
CY
Bit6
-
TR1
C/ T
SM1
-
-
AC
Bit5
-
TF0
M1
SM2
-
-
F0
Bit4 Bit3 Bit2 Bit1 Bit0
- GF1 GF0 PD IDLE
TR0 IE1 IT1 IE0 IT0
M0 GATE C / T M1
M0
REN TB8 RB8
TI
RI
ES ET1 EX1 ET0 EX0
PS PT1 PX1 PT0 PX0
RS1 RS0
OV
F1
P
- : This Bit Location is reserved
Bit manipulation is available
Bit manipulation is not available
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97C2051 arduino
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8-Bit CMOS Microcontorller
GMS97C2051/L2051
Programming The EPROM
The GMS97C2051/L2051 is programmed by using a
modified Quick-Pulse ProgrammingTM algorithm. It
differs from older methods in the value used for VPP
(programming supply voltage) and in the width and
number of the P3.2( PROG ) .
The GMS97C2051/L2051 contains two signature
bytes that can be read and used by an EPROM pro-
gramming system to identify the device. The signature
bytes identify the device as an manufactured by HME .
Table 10 shows the logic levels for reading the signa-
ture byte, and for programming the program memory,
the encryption table, and the security bits. The circuit
configuration and waveforms for quick-pulse pro-
gramming are shown in Figures 5 and Figure 8.
Figure 6 shows the circuit configuration for normal
program memory verification.
EPROM Programming and Verification
Internal Address Counter :
The GMS97C2051/L2051 contains an internal EPROM
address counter which is always set to 07FFH on the
rising edge of RST after setting P3.0 to ‘H’ and is ad-
vanced by applying continuous level transition to pin
P3.0.
Programming Algorithm :
To program the GMS97C2051/L2051, the following
sequence is recommended.
1. Power-up Sequence
Apply power between VCC and GND pins with
crystal oscillation.
Set P3.0 to ‘H’.
Set RST to GND.
With all other pins floating, wait for greater than
10ms.
2. Set pin RST to ‘H’ and pin P3.2 to ‘H’.
3. Apply the appropriate combination of ‘H’ or ‘L’
logic levels to pins P3.3, P3.4, P3.5, P3.7 to select
one of the programming operations shown in the
EPROM Programming Modes. (Table 10).
To program and verify the array
4. The P3.0 level is pulled ‘L’ and apply data for
code byte at location 0000H to P1.0 to P1.7
5. Raise RST to 12.75V to enable pr ogramming.
6. The P3.2( PROG ) is pulsed low 10 times as shown
in Figure 8. Each programming pulse is low for
100us(±10us) and high for a minimum of 10us.
7. To verify the programmed data, lower RST from
12.75V to logic ‘H’ level and set pins P3.3 to P3.7
to the appropriate levels. Output data can be read
at the port P1 pins. At this time P3.0 should not be
changed.
8. To program a byte at the next address location,
P3.0 level transition is needed to advance the
internal address counter. Apply new data to the
port P1 pins.
9. Repeat step 5 through 8, changing data and
advancing the address counter for the entire 2K
bytes array.
Program Verify :
If lock bits LB1 and LB2 have not been programmed,
code data can be read back via port P1 pins.
1. Set the internal address counter to 07FFH by
bringing RST from ‘L’ to ‘H’ and reset the
internal address counter to 0000H by bringing P3.0
from ‘H’ to ‘L’.
2. Apply the appropriate control signals for Read
Code data to pins P3.3, P3.4, P3.5, P3.7 and read
the output data at the port P1 pins.
3. The P3.0 level transition is taken to advance the
internal address counter.
4. Read the next code data byte at the port P1 pins.
5. Repeat step 3 and 4 until the entire array is read.
Program Memory Lock Bits
The two-level Program Lock system consists of 2 Lock
bits and a 32-byte Encryption Array which are used to
protect the program memory against software piracy.
Encryption Array :
Within the EPROM array are 32 bytes of Encryption
Array that are initially unprogrammed (all 1s). Every
time that a byte is addressed during a verify, address
lines are used to select a byte of the Encryption array.
This byte is then exclusive-NORed (XNOR) with the
code byte, creating an Encrypted Verify byte.
The algorithm, with the array in the unprogrammed
state (all 1s), will return the code in its original, un-
modified form. It is recommended that whenever the
Encryption Array is used, at least one of the Lock Bits
be programmed as well.
11 HYUNDAI MicroElectonics

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