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PDF AT89LP214 Datasheet ( Hoja de datos )

Número de pieza AT89LP214
Descripción 8-bit Microcontroller
Fabricantes ATMEL Corporation 
Logotipo ATMEL Corporation Logotipo
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AT89LP214 datasheet

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AT89LP214 pdf
4. Block Diagram
Figure 4-1. AT89LP213 Block Diagram
AT89LP213/214
Single Cycle
8051 CPU
2KB Flash
128 Bytes
RAM
Port 3
Configurable I/O
Port 1
Configurable I/O
General-purpose
Interrupt
SPI
Timer 0
Timer 1
Analog
Comparator
Watchdog
Timer
On-Chip
RC Oscillator
CPU Clock Configurable
Oscillator
Figure 4-2. AT89LP214 Block Diagram
Crystal or
Resonator
Single Cycle
8051 CPU
2KB Flash
128 Bytes
RAM
Port 3
Configurable I/O
Port 1
Configurable I/O
General-purpose
Interrupt
CPU Clock
UART
SPI
Timer 0
Timer 1
Analog
Comparator
Watchdog
Timer
On-Chip
RC Oscillator
Configurable
Oscillator
Crystal or
Resonator
3538E–MICRO–11/10
5

5 Page

AT89LP214 arduino
8. Enhanced CPU
The AT89LP213/214 uses an enhanced 8051 CPU that runs at 6 to 12 times the speed of stan-
dard 8051 devices (or 3 to 6 times the speed of X2 8051 devices). The increase in performance
is due to two factors. First, the CPU fetches one instruction byte from the code memory every
clock cycle. Second, the CPU uses a simple two-stage pipeline to fetch and execute instructions
in parallel. This basic pipelining concept allows the CPU to obtain up to 1 MIPS per MHz. A sim-
ple example is shown in Figure 8-1.
The MCS-51 instruction set allows for instructions of variable length from 1 to 3 bytes. In a sin-
gle-clock-per-byte-fetch system this means each instruction takes at least as many clocks as it
has bytes to execute. The majority of instructions in the AT89LP213/214 follow this rule: the
instruction execution time in clock cycles equals the number of bytes per instruction with a
few exceptions. Branches and Calls require an additional cycle to compute the target address
and some other complex instructions require multiple cycles. See “Instruction Set Summary” on
page 60 for more detailed information on individual instructions. Figures 8-2 and 8-3 show
examples of 1- and 2-byte instructions.
Figure 8-1. Parallel Instruction Fetches and Executions
Tn Tn+1
Tn+2
System Clock
nth Instruction
Fetch
Execute
(n+1)th Instruction
Fetch
Execute
(n+2)th Instruction
Fetch
Figure 8-2. Single-cycle ALU Operation (Example: INC R0)
T1 T2
System Clock
Total Execution Time
Register Operand Fetch
ALU Operation Execute
Result Write Back
Fetch Next Instruction
T3
10 AT89LP213/214
3538E–MICRO–11/10

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