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PDF AT89LP4052 Datasheet ( Hoja de datos )

Número de pieza AT89LP4052
Descripción 8-bit Microcontroller
Fabricantes ATMEL Corporation 
Logotipo ATMEL Corporation Logotipo

Total 30 Páginas
		
AT89LP4052 Hoja de datos, Descripción, Manual
Features
Compatible with MCS®51 Products
20 MIPS Throughput at 20 MHz Clock Frequency and 2.4V, 85°C Operating Conditions
Single Clock Cycle per Byte Fetch
2/4K Bytes of In-System Programmable (ISP) Flash Memory
– Serial Interface for Program Downloading
– 32-byte Fast Page Programming Mode
– 32-byte User Signature Array
2.4V to 5.5V VCC Operating Range
Fully Static Operation: 0 Hz to 20 MHz
2-level Program Memory Lock
256 x 8 Internal RAM
Hardware Multiplier
15 Programmable I/O Lines
Configurable I/O with Quasi-bidirectional, Input, Push-pull Output, and
Open-drain Modes
Enhanced UART with Automatic Address Recognition and Framing Error Detection
Enhanced SPI with Double-buffered Send/Receive
Programmable Watchdog Timer with Software Reset
4-level Interrupt Priority
Analog Comparator with Selectable Interrupt and Debouncing
Two 16-bit Enhanced Timer/Counters with 8-bit PWM
Brown-out Detector and Power-off Flag
Internal Power-on Reset
Low Power Idle and Power-down Modes
Interrupt Recovery from Power-down Mode
8-bit
Microcontroller
with 2/4-Kbyte
Flash
AT89LP2052
AT89LP4052
1. Description
The AT89LP2052/LP4052 is a low-power, high-performance CMOS 8-bit microcon-
troller with 2/4K bytes of In-System Programmable Flash memory. The device is
manufactured using Atmel's high-density nonvolatile memory technology and is com-
patible with the industry-standard MCS-51 instruction set. The AT89LP2052/LP4052
is built around an enhanced CPU core that can fetch a single byte from memory every
clock cycle. In the classic 8051 architecture, each fetch required 6 clock cycles, forc-
ing instructions to execute in 12, 24 or 48 clock cycles. In the AT89LP2052/LP4052
CPU, instructions need only 1 to 4 clock cycles providing 6 to 12 times more through-
put than the standard 8051. Seventy percent of instructions need only as many clock
cycles as they have bytes to execute, and most of the remaining instructions require
only one additional clock. The enhanced CPU core is capable of 20 MIPS throughput
whereas the classic 8051 CPU can deliver only 4 MIPS at the same current consump-
tion. Conversely, at the same throughput as the classic 8051, the new CPU core runs
at a much lower speed and thereby greatly reduces power consumption.
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AT89LP4052 pdf
Figure 5-1. Program Memory Map
AT89LP2052/LP4052
0FFF
07FF
0000
Program Memory
AT89LP2052
Program Memory
AT89LP4052
0000
5.2 Data Memory
The AT89LP2052/LP4052 contains 256 bytes of general SRAM data memory plus 128 bytes of
I/O memory. The lower 128 bytes of data memory may be accessed through both direct and
indirect addressing. The upper 128 bytes of data memory and the 128 bytes of I/O memory
share the same address space (see Figure 5-2). The upper 128 bytes of data memory may only
be accessed using indirect addressing. The I/O memory can only be accessed through direct
addressing and contains the Special Function Registers (SFRs). The lowest 32 bytes of data
memory are grouped into 4 banks of 8 registers each. The RS0 and RS1 bits (PSW.3 and
PSW.4) select which register bank is in use. Instructions using register addressing will only
access the currently specified bank. The AT89LP2052/LP4052 does not support external data
memory.
Figure 5-2. Data Memory Map
FFH
Upper
128
80H
7FH
Lower
128
Accessible
By Indirect
Addressing
Only
Accessible
By Direct and
Indirect
Addressing
0
Accessible
By Direct
Addressing
FFH
80H
Special
Function
Registers
Ports
Status and
Control Bits
Timers
Registers
Stack Pointer
Accumulator
(Etc.)
3547J–MICRO–10/09
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AT89LP4052 arduino
AT89LP2052/LP4052
11. Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be
configured for use as an on-chip oscillator, as shown in Figure 11-1. Either a quartz crystal or
ceramic resonator may be used. For frequencies above 16MHz it is recommended that C1 be
replaced with R1 for improved startup performance. Note that the internal structure of the
devices adds about 10 pF of capacitance to both XTAL1 and XTAL2. The total capacitance on
XTAL1 or XTAL2, including the external load capacitor (C1/C2) plus internal device load, board
trace and crystal loadings, should not exceed 20 pF. Figure 11-2, 11-3, 11-4 and 11-5 illustrate
the relationship between clock loading and the respective resulting clock amplitudes.
Figure 11-1. Oscillator Connections
C2
C2
~10 pF
~10 pF
C1 R1
~10 pF
~10 pF
(A) Low Frequency
Note:
C1, C2 = 0–10 pF for Crystals
= 0–10 pF for Ceramic Resonators
R1 = 4–5 MΩ
Figure 11-2. Quartz Crystal Clock Source (A)
(B) High Frequency
Quartz Crystal Clock Input
7
6 C1=C2=0pF
C1=C2=5pF
5 C1=C2=10pF
4
3
2
1
0
0 4 8 12 16 20 24
Frequency (MHz)
3547J–MICRO–10/09
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