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PDF AT89LP4052 Datasheet ( Hoja de datos )

Número de pieza AT89LP4052
Descripción 8-bit Microcontroller
Fabricantes ATMEL Corporation 
Logotipo ATMEL Corporation Logotipo
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AT89LP4052 datasheet

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AT89LP4052 pdf
Figure 5-1. Program Memory Map
AT89LP2052/LP4052
0FFF
07FF
0000
Program Memory
AT89LP2052
Program Memory
AT89LP4052
0000
5.2 Data Memory
The AT89LP2052/LP4052 contains 256 bytes of general SRAM data memory plus 128 bytes of
I/O memory. The lower 128 bytes of data memory may be accessed through both direct and
indirect addressing. The upper 128 bytes of data memory and the 128 bytes of I/O memory
share the same address space (see Figure 5-2). The upper 128 bytes of data memory may only
be accessed using indirect addressing. The I/O memory can only be accessed through direct
addressing and contains the Special Function Registers (SFRs). The lowest 32 bytes of data
memory are grouped into 4 banks of 8 registers each. The RS0 and RS1 bits (PSW.3 and
PSW.4) select which register bank is in use. Instructions using register addressing will only
access the currently specified bank. The AT89LP2052/LP4052 does not support external data
memory.
Figure 5-2. Data Memory Map
FFH
Upper
128
80H
7FH
Lower
128
Accessible
By Indirect
Addressing
Only
Accessible
By Direct and
Indirect
Addressing
0
Accessible
By Direct
Addressing
FFH
80H
Special
Function
Registers
Ports
Status and
Control Bits
Timers
Registers
Stack Pointer
Accumulator
(Etc.)
3547J–MICRO–10/09
5

5 Page

AT89LP4052 arduino
9. Restrictions on Certain Instructions
The AT89LP2052/LP4052 is an economical and cost-effective member of Atmel's growing fam-
ily of microcontrollers. It contains 2/4K bytes of Flash program memory. It is fully compatible with
the MCS-51 architecture, and can be programmed using the MCS-51 instruction set. However,
there are a few considerations one must keep in mind when utilizing certain instructions to pro-
gram this device. All the instructions related to jumping or branching should be restricted such
that the destination address falls within the physical program memory space of the device, which
is 2K bytes for the AT89LP2052 and 4K bytes for the AT89LP4052. This should be the responsi-
bility of the software programmer. For example, LJMP 7E0H would be a valid instruction for the
AT89LP2052 (with 2K bytes of memory), whereas LJMP 900H would not.
9.1 Branching Instructions
The LCALL, LJMP, ACALL, AJMP, SJMP, and JMP @A+DPTR unconditional branching instruc-
tions will execute correctly as long as the programmer keeps in mind that the destination
branching address must fall within the physical boundaries of the program memory size (loca-
tions 000H to 7FFH for the AT89LP2052, 000H to FFFH for the AT89LP4052). Violating the
physical space limits may cause unknown program behavior. With the CJNE [...], DJNZ [...], JB,
JNB, JC, JNC, JBC, JZ, and JNZ conditional branching instructions, the same previous rule
applies. Again, violating the memory boundaries may cause erratic execution. For applications
involving interrupts, the normal interrupt service routine address locations of the 8051 family
architecture have been preserved.
9.2 MOVX-related Instructions, Data Memory
External DATA memory access is not supported in this device, nor is external PROGRAM mem-
ory execution. Therefore, no MOVX [...] instructions should be included in the program. A typical
8051 assembler will still assemble instructions, even if they are written in violation of the restric-
tions mentioned above. It is the responsibility of the user to know the physical features and
limitations of the device being used and to adjust the instructions used accordingly.
10. System Clock
The system clock is generated directly from one of two selectable clock sources. The two
sources are the on-chip crystal oscillator and external clock source. No internal clock division is
used to generate the CPU clock from the system clock.
10.1
Crystal Oscillator
When enabled, the internal inverting oscillator amplifier is connected between XTAL1 and
XTAL2 for connection to an external quartz crystal or ceramic resonator. When using the crystal
oscillator, XTAL2 should not be used to drive a board-level clock.
10.2
External Clock Source
The external clock option is selected by setting the Oscillator Bypass fuse. This disables the
amplifier and allows XTAL1 to be driven directly by the clock source. XTAL2 may be left
unconnected.
10.3
System Clock Out
When the System Clock Out fuse is enabled, P3.7 will output the system clock with no division
using the push-pull output mode. During Power-down the system clock will output as “1”.
10 AT89LP2052/LP4052
3547J–MICRO–10/09

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