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PDF K4M56323LE Data sheet ( Hoja de datos )
| Número de pieza | K4M56323LE | |
| Descripción | 2M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA | |
| Fabricantes | Samsung semiconductor | |
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K4M56323LE - M(E)E/N/S/C/L/R
Mobile-SDRAM
2M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA
FEATURES
• 2.5V power supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (4K cycle).
• Commercial Temperature Operation (-25°C ~ 70°C).
• Extended Temperature Operation (-25°C ~ 85°C).
• 2Chips DDP 90Balls FBGA with 0.8mm ball pitch
( -MXXX : Leaded, -EXXX : Lead Free).
GENERAL DESCRIPTION
The K4M56323LE is 268,435,456 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits,
fabricated with SAMSUNG’s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth and high per-
formance memory system applications.
ORDERING INFORMATION
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Part No.
Max Freq.
Interface
K4M56323LE-M(E)E/N/S/C/L/R80
K4M56323LE-M(E)E/N/S/C/L/R1H
125MHz(CL=3)
105MHz(CL=2)
LVCMOS
K4M56323LE-M(E)E/N/S/C/L/R1L
105MHz(CL=3)*1
- M(E)E/N/S : Normal / Low / Super Low Power, Extended Temperature(-25°C ~ 85°C)
- M(E)C/L/R : Normal / Low / Super Low Power, Commercial Temperature(-25°C ~ 70°C)
Package
90 FBGA
Leaded (Lead Free)
NOTES :
1. In case of 40MHz Frequency, CL1 can be supported.
2. Samsung shall not offer for sale or sell either directly or through and third-party proxy, and DRAM memory products that include "Multi-Die Plastic
DRAM" for use as components in general and scientific computers such as, by way of example, mainframes, servers, work stations or desk top
computers for the first three years of five year term of this license. Nothing herein limits the rights of Samsung to use Multi-Die Plastic DRAM in other
products or other applications under paragrangh such as mobile, telecom or non-computer application(which include by way of example laptop or
notebook computers, cell phones, televisions or visual monitors)
Violation may subject the customer to legal claims and also excludes any warranty against infringement from Samsung." .
3. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific
purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
DataShee
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K4M56323LE - M(E)E/N/S/C/L/R
Mobile-SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)
Parameter
Symbol
Test Condition
Version
-80 -1H -1L
Unit Note
Operating Current
(One Bank Active)
Burst length = 1
ICC1 tRC ≥ tRC(min)
IO = 0 mA
140 140 130 mA 1
Precharge Standby Current in ICC2P CKE ≤ VIL(max), tCC = 10ns
power-down mode
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞
Precharge Standby Current
in non power-down mode
ICC2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC2NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
1.2
1.2
20
10
mA
mA
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
ICC3P CKE ≤ VIL(max), tCC = 10ns
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC3NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
8
8
45
40
mA
mA
mA
Operating Current
(Burst Mode)
IO = 0 mA
ICC4
Page burst
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180 150 150 mA 1
Refresh Current
ICC5 tRC ≥ tRC(min)
-E/C
-N/L
Self Refresh Current
ICC6 CKE ≤ 0.2V
-S/R
Internal TCSR
4Banks
2Banks
1Bank
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Internal TCSR can be supported.
In commercial Temp : Max 40°C/Max 70°C, In extended Temp : Max 40°C/Max 85°C
4. K4M56323LE-M(E)E/C**
5. K4M56323LE-M(E)N/L**
6. K4M56323LE-M(E)S/R**
7. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
300 290 270 mA
1500
1000
uA
Max 40 Max 85/70 °C
600 1000
500 800 uA
450 700
2
4
5
3
6
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K4M56323LE - M(E)E/N/S/C/L/R
Mobile-SDRAM
Partial Array Self Refresh
1. In order to save power consumption, Mobile SDRAM has PASR option.
2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode : 4 Banks(256Mb), 2 Banks(128Mb) and 1 Bank(64Mb).
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BA1=0 BA1=0
BA0=0 BA0=1
BA1=0 BA1=0
BA0=0 BA0=1
BA1=0 BA1=0
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
- 4 Banks
- 2 Banks
- 1 Bank
Partial Self Refresh Area
Temperature Compensated Self Refresh
1. In order to save power consumption, Mobile-DRAM includes the internal temperature sensor and control units to control the self
refresh cycle automatically according to the two temperature range : Max 40 °C and Max 85 °C(for Extended), Max 70 °C(for
Commercial).
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
Self Refresh Current (Icc6)
Temperature Range
- E/C
- N/L
Max 85/70 °C
Max 40 °C
1500
1000
- S/R
4 Banks
2 Banks
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1000
800
600 500
1 Bank
700
450
Unit
uA
DataShee
B. POWER UP SEQUENCE
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
- Apply VDD before or at the same time as VDDQ.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS.
EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used.
The default state without EMRS command issued is the full driver strength and all 4 banks refreshed.
The device is now ready for the operation selected by EMRS.
For operating with DS or PASR, set DS or PASR mode in EMRS setting stage.
In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not
needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.
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| PDF Descargar | [ Datasheet K4M56323LE.PDF ] | |
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