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PDF K4M563233G Data sheet ( Hoja de datos )
| Número de pieza | K4M563233G | |
| Descripción | 2M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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K4M563233G - F(H)N/G/L/F
Mobile-SDRAM
2M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA
FEATURES
• 3.0V & 3.3V power supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (4K cycle).
• Commercial Temperature Operation (-25°C ~ 70°C).
• Extended Temperature Operation (-25°C ~ 85°C).
• 90Balls FBGA ( -FXXX -Pb, -HXXX -Pb Free).
GENERAL DESCRIPTION
The K4M563233G is 268,435,456 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits,
fabricated with SAMSUNG’s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth and high per-
formance memory system applications.
ORDERING INFORMATION
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Part No.
Max Freq.
K4M563233G-F(H)N/G/L/F60
166MHz(CL=3)
K4M563233G-F(H)N/G/L/F75
133MHz(CL=3), 111MHz(CL=2)
K4M563233G-F(H)N/G/L/F7L*1
133MHz(CL=3), 83MHz(CL=2)
- F(H)N/G : Low Power, Extended Temperature(-25°C ~ 85°C)
- F(H)L/F : Low Power, Commercial Temperature(-25°C ~ 70°C)
NOTES :
1. In case of 40MHz Frequency, CL1 can be supported.
Interface
LVCMOS
Package
90 FBGA Pb
(Pb Free)
DataShee
Address configuration
Organization
8Mx32
Bank
BA0,BA1
Row
A0 - A11
Column Address
A0 - A8
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PRO-
VIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could
result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or pro-
visions may apply.
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K4M563233G - F(H)N/G/L/F
Mobile-SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)
Parameter
Symbol
Test Condition
Version
-60 -75 -7L
Unit Note
Operating Current
(One Bank Active)
Burst length = 1
ICC1 tRC ≥ tRC(min)
IO = 0 mA
100 90
90 mA 1
Precharge Standby Current in ICC2P CKE ≤ VIL(max), tCC = 10ns
power-down mode
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞
Precharge Standby Current
in non power-down mode
ICC2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC2NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
1.0
1.0
15
5
mA
mA
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
ICC3P CKE ≤ VIL(max), tCC = 10ns
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC3NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
8
8
25
15
mA
mA
mA
Operating Current
(Burst Mode)
IO = 0 mA
ICC4 Page burst
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160 130 130 mA 1
Refresh Current
Self Refresh Current
ICC5 tRC ≥ tRC(min)
ICC6 CKE ≤ 0.2V
-G/F
-N/L
Internal TCSR
Full Array
1/2 of Full Array
1/4 of Full Array
180 160 160
600
45 *5
450
85/70
600
400 450
350 400
mA
uA
°C
uA
2
3
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Internal TCSR can be supported.
In commercial Temp : 45°C/70°C, In extended Temp : 45°C/85°C
4. It has +/-5 °C tolerance.
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
DataShee
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K4M563233G - F(H)N/G/L/F
Mobile-SDRAM
Partial Array Self Refresh
1. In order to save power consumption, Mobile SDRAM has PASR option.
2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode : Full Array, 1/2 of Full Array and 1/4 of Full Array.
BA1=0 BA1=0
BA0=0 BA0=1
BA1=0 BA1=0
BA0=0 BA0=1
BA1=0 BA1=0
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
- Full Array
- 1/2 Array
- 1/4 Array
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Partial Self Refresh Area
Internal Temperature Compensated Self Refresh (TCSR)
1. In order to save power consumption, Mobile-SDRAM includes the internal temperature sensor and control units to control the
self refresh cycle automatically according to the two temperature range ; 45 °C and 85 °C(for Extended), 70 °C(for
Commercial).
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
3. It has +/-5 °C tolerance.
Self Refresh Current (Icc6)
Temperature Range
-N/L
-G/F
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Full Array
1/2 of Full Array
1/4 of Full Array
Unit
45 °C *3
450 400 350
600 uA
85/70 °C
600 450 400
DataShee
B. POWER UP SEQUENCE
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
- Apply VDD before or at the same time as VDDQ.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS.
For operating with DS or PASR, set DS or PASR mode in EMRS setting stage.
In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not
needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.
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| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet K4M563233G.PDF ] | |
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