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PDF RD38F4460LVY Data sheet ( Hoja de datos )
| Número de pieza | RD38F4460LVY | |
| Descripción | Wireless Memory System | |
| Fabricantes | Intel | |
| Logotipo |  |
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Intel StrataFlash Wireless Memory
System (LV18 SCSP)
1024-Mbit LVX Family with LPSDRAM
Datasheet
Product Features
■ Device Memory Architecture
■ Code Segment Flash Read Performance
— Flash die density: 128-, 256-Mbit
— 85 ns initial access
— LPSDRAM die density: 128-, 256-Mbit — 25 ns Asynchronous Page read
— Top or Bottom parameter flash
configuration
— 14 ns Synchronous read (tCHQV)
— 54 MHz (max.) CLK
■ Device Voltage
■ Data Segment Flash Performance
— Core: VCC = 1.8 V (typ.)
— 170 ns initial access
— I/O: VCCQ = 1.8 V (typ.)
— 55 ns Asynchronous Page read
■ Device Common Performance
■ Code Segment Flash Architecture
— Buffered EFP: 5µs / Byte (typ.) per die
— Hardware Read-While-Write/Erase
— Buffer Program: 7µs / Byte (typ.) per die — Multiple 8-Mbit / 16-Mbit partition sizes
— Concurrent Buffered EFP:
6.4-Mbps effective with 4 flash dies
— 2-Kbit One-Time-Programmable
Protection Register
■ Device Common ArchitecDtuartae Sheet4U.com■ Data Segment Flash Architecture
— Asymmetrical blocking structure
— Software Read-While-Write/Erase
— 16-KWord parameter blocks (Top or
Bottom); 64-KWord main blocks
— Zero-latency block locking
— Absolute write protection with block
lock down using F-VPP and F-WP#
■ Device Packaging
— 103 active balls; 9 x 12 ball matrix
— Area: 9 x 11 mm to 11 x 11 mm
— Height: 1.4 mm
■ SDRAM Architecture and Performance
— Clock rate: 105 MHz
— Single partition size die
■ Flash Software
— Intel FDI, Intel PSM, and Intel
VFM
— Common Flash Interface
— Basic/Extended Command Set
■ Quality and Reliability
— Extended temperature: –25 °C to +85 °C
— Minimum 100 K flash block erase cycle
— 0.13 µm ETOX VIII flash technology
— Four internal banks
— Burst Length: 1, 2, 4, 8, or full page
Intel StrataFlash® Wireless Memory System (LV18 SCSP) with Low-Power SDRAM (LVX
family) offers a variety of high performance code segment, large embedded data segment, and
low-power SDRAM combinations in a common package on 0.13 µm ETOX™ VIII flash
technology. The LVX family integrates up to two code segment flash dies, two data segment flash
dies, and two low-power SDRAM dies or one SRAM die in a common x16D Performance ballout.
Notice: This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the
latest datasheet before finalizing a design.
300945-006
October 2004
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Revision History
Contents
et4U.com
Date
February, 2004
February, 2004
April, 2004
June, 2004
July, 2004
October, 2004
Revision
-001
-002
-003
-004
-005
-006
Description
Initial release.
Corrected information in the Memory Map table, code and data
segments, bottom parameter.
Corrected errors in Table 1 and Table 26. The package
dimension of part RD48F4444LVYBB0 RD48F4444LVYTB0
now reads 11x11x1.4 instead of 9x11x1.4.
Updated Table 1 and Table 26. Added line item
RD38F4460LVYGB0. Added G as an option to Figure 29 -
Ordering Information. Added Figure 6, a top-top memory map
diagram. Added top/top configuration feature to the title page
“Product Features”.
Added the mechanical specification diagram, Figure 5 for the
11x11x1.4 mm option.
Added line items 256L18/256V18/256SD, 256L18/256L18/
256V18/256SD, and 256L18/256V18/256V18/256SD to the
following tables:
* Table 1 “Available Product Ordering Information for the
LVX Family with LPSDRAM” on page 12
* Table 26 “LVX Family with LPSDRAM: Available Product
Ordering Information” on page 57. .
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LVX Family
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2.0 Functional Overview
This section provides an overview of the features and capabilities of Intel StrataFlash® Wireless
Memory System (LV18 SCSP) with Low-Power SDRAM LVX family; hereafter in this document,
this device is called the LVX family with LPSDRAM device.
2.1 Product Description
The LVX family with LPSDRAM device incorporates flash dies used as code segment flash die
and large embedded data segment flash die, along with LPSDRAM for a high performance, cost-
effective high density solution. This stacked device utilizes the latest Intel StrataFlash® Wireless
Memory System on 0.13 µm ETOX™ VIII process technology.
The code segment flash is a high performance, multi-partition, synchronous burst-mode Read-
While-Write (RWW) or Read-While-Erase (RWE), while the large embedded data segment is a
cost efficient, single partition, asynchronous memory die.
The package for this device is available in a x16D Performance ballout, supporting flash-only or
flash with LPSDRAM stacked memory combinations. The Intel® SCSP package in a x16D
performance ballout with a 0.8 mm ball pitch, 9 x 12 active ball matrix supports a memory
subsystem up to 105 MHz on a x16-bit bus width. See Figure 1, “LVX Family with LPSDRAM
Device Block Diagram” on page 11.
Figure 1. LVX Family with LPSDRAM Device Block Diagram
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LVX Family
Flash (Code/Data) Segment
F1-CE#
F-WP1#
F-CLK
ADV#
F-WP2#
WAIT
OE#
F3-CE#
WE#
DQ[15:0]
A[MAX:MIN]
D-DM1 / R-UB#
D-DM0 / R-LB#
S-CS1#
S-CS2
S-VCC
Flash Die #1
(128- or 256-Mbit)
Flash Die #2
(128- or 256-Mbit)
Flash Die #3
(128- or 256-Mbit)
Flash Die #4
(128- or 256-Mbit)
xRAM Segment
SRAM Die #1
(8-Mbit)
LPSDRAM Die #1
(128/256-Mbit)
LPSDRAM Die #2
(128/256-Mbit)
F2-CE#
F-RST#
F-VCC
F-VPP
F4-CE#
VCCQ
VSS
R1-CS#
R2-CS#
D-BA[1:0]
D-CAS#
D-RAS#
R-CLK
D-CKE
R-VCC
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