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PDF RD38F4050L0Z Data sheet ( Hoja de datos )
| Número de pieza | RD38F4050L0Z | |
| Descripción | (RD38F4455LVY / RD38F4050L0Z) Wireless Memory System | |
| Fabricantes | Intel | |
| Logotipo |  |
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Intel StrataFlash£ Wireless Memory
System (LV18/LV30 SCSP)
768-Mbit LVQ Family with Asynchronous Static RAM
Datasheet
Product Features
■ Device Architecture
■ xRAM Performance
— Code and data segment: 128- and 256-
Mbit density; PSRAM: 32- and 64-Mbit
density; SRAM: 8 Mbit density.
— PSRAM at 1.8 V I/O : 85 ns initial
access, 30 ns async page reads; 65 ns
initial access, 18 ns async page.
— Top or bottom parameter configuration. — SRAM at 1.8 or 3.0 V I/O: 70 ns initial
— Asymmetrical blocking structure.
access.
— 16-KWord parameter blocks (Top or
■ Flash Performance
Bottom); 64-K Word main blocks.
— Code Segment at 1.8 V I/O: 85 ns initial
— Zero-latency block locking.
access; 25 ns async page read; 14 ns
— Absolute write protection with block
sync reads (tCHQV); 54 MHz CLK.
lock down using F-WP#.
— Data Segment at 1.8 V I/O: 170 ns initial
access; 55 ns async page read.
■ Device Voltage
— Core: VCC = 1.8 V (typ).
■ Flash Architecture
— Hardware Read-While-Write/Erase.
— I/O: VCCQ = 1.8 V or 3.0DVa(ttaySph).eet4U.com— 8-Mbit or 16-Mbit Multi-Partition.
■ Device Concurrent Operations (3 Dies)
— Buffered EFP: 600 KB per second.
— 2-Kbit One-Time Programmable (OTP)
Protection Register.
— Erase Performance: 384 KB per second
(main blocks).
— Software Read-While-Write/Erase.
■ Device Packaging
— Single Full-Die Partition size.
— 88 balls (8 x 10 active ball matrix).
— Area: 8 x 10 mm or 8 x 11 mm.
■ Flash Software
— Intel£ FDI, Intel£ PSM, and Intel£
VFM.
— Height: 1.0 mm to 1.4 mm.
— Common Flash Interface (CFI).
■ Quality and Reliability
— Extended Temp: –25 °C to +85 °C.
— Basic/Extended Command Set.
— Minimum 100 K flash block erase cycle.
The Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP); 768-Mbit LVQ Family
with Asynchronous Static RAM device offers a high performance code and large embedded data
segment plus RAM combination in a common package with electrical QUAD+ ballout on 0.13
µm ETOX™ VIII flash technology. The code segment flash die features 1.8 V low-power
operations with flexible, multi-partition, dual operation Read-While-Write / Read-While-Erase,
asynchronous and synchronous burst reads at 54 MHz. The data segment flash die features 1.8 V
low-power operations optimized for cost sensitive asynchronous data applications. This device
integrates up to three flash dies, two PSRAM dies, and one SRAM die in a low-profile package
compatible with other SCSP families using the QUAD+ ballout package.
Notice: This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the lat-
est datasheet before finalizing a design.
253852-002
December 2003
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768-Mbit LVQ Family with Asynchronous Static RAM
1.0
1.1
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Introduction
This document provides information about the Intel StrataFlash® Wireless Memory System (LV18/
LV30 SCSP); 768-Mbit LVQ Family with Asynchronous Static RAM device, including
information on the features, characteristics, operations, and specifications for:
• Code and data segment flash dies
• SRAM and PSRAM dies
The intent of this document is to provide information where this 768-Mbit LVQ Family with
Asynchronous Static RAM Stacked Chip Scale Package (SCSP) device differs from the Intel
StrataFlash® Wireless Memory System (LV18/LV30 SCSP); 1024-Mbit LV Family device. Refer
to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP; 1024-
Mbit LV Family Datasheet (order number 253854) for flash product details not included in this
document.
Nomenclature
0x
0b
Byte
CFI
DU
ETOX
k (noun)
Kb
KB
Kword
M (noun)
Mb
MB
OTP
RCR
RFU
SCSP
SR
SRD
Word
1.8 V Core
1.8 V I/O
Asserted
Deasserted
High-Z
Low-Z
Hexadecimal prefix
Binary prefix
8 bits
Common Flash Interface
Don’t Use
EPROM TunDnaetlaOSxhiedeet4U.com
1 thousand
1024 bits
1024 bytes
1024 words
1 million
1,048,576 bits
1,048,576 bytes
One-time Programmable
Read Configuration Register
Reserved for Future Use
Stacked Chip Scale Package
Status Register
Status Register Data
16 bits
range of 1.7 V – 1.95 V
range of 1.7 V – 1.95 V
Signal with logical voltage level VIL, or enabled
Signal with logical voltage level VIH, or disabled
Tri-stated or High Impedance
Driven
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768-Mbit LVQ Family with Asynchronous Static RAM
3.0 Package Information
The 768-Mbit LVQ Family with Asynchronous Static RAM device is available with various die
combinations in both the standard Stacked Chip Scale Package (SCSP) and the Intel® Ultra-Thin
Stacked Chip Scale Package (Intel® UT-SCSP).
3.1 One- and Two-Die SCSP
Figure 2. Mechanical Specifications for One/Two-Die SCSP (8x10 mm)
8x10x1.2Q
A1 Index
Mark
12
345 678
S1
8 7 6 5 4 3 21
S2
AA
BB
CC
DD
EE
F
DF
e
GG
HH
JJ
KK
L DataSheetL4U.com
MM
b
E
Top View - Ball Down
A2
A1
Bottom View - Ball
Up
A
Y
Draw ing not to scale.
DataShee
Di mens ions
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Length
Package Body Width
Pitch
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball A1 Distance Along E
Corner to Ball A1 Distance Along D
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Datasheet
D a t a S h e4e tU . c o m
Symbol
A
A1
A2
b
D
E
e
N
Y
S1
S2
Mil li mete rs
Min Nom Max Notes Min
1.200
0.200
0.0079
0.860
0.325 0.375 0.425
0.0128
9.900 10.000 10.100
0.3898
7.900 8.000 8.100
0.3110
0.800
88
0.100
1.100 1.200 1.300
0.0433
0.500 0.600 0.700
0.0197
Inches
Nom
0.0339
0.0148
0.3937
0.3150
0.0315
88
0.0472
0.0236
Max
0.0472
0.0167
0.3976
0.3189
0.0039
0.0512
0.0276
11
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