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PDF NL6448BC33-53 Data sheet ( Hoja de datos )
| Número de pieza | NL6448BC33-53 | |
| Descripción | TFT COLOR LCD MODULE | |
| Fabricantes | NEC | |
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TFT COLOR LCD MODULE
NL6448BC33-53
26cm (10.4 Type)
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PRELIMINARY DATA SHEET
(2nd edition)
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All information is subject to change without notice.
Please confirm the delivery specification before starting to
design your system.
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Document Number: DOD-M- 1309 (2nd edition)
Published date: January 2003 CP(N)
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1 ã NEC Corporation
2003 All rights reserved.
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NL6448BC33-53
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2. GENERAL SPECIFICATIONS
Display area
211.2 (W) × 158.4 (H) mm (typ.)
Diagonal size of display
26 cm (10.4 inches)
Drive system
a-Si TFT active matrix
Display color
262,144 colors
Pixel
Pixel arrangement
640 (H) × 480 (V) pixels
RGB (Red dot, Green dot, Blue dot) vertical stripe
Dot pitch
Pixel pitch
0.11 (W) × 0.33 (H) mm
0.33 (W) × 0.33 (H) mm
Module size
Weight
243.0 (W) × 185.1 (H) × 10.5 (D) mm (typ.)
475 g (typ.)
Contrast ratio
300:1 (typ.)
Viewing angle
Designed viewing direction
At the contrast ratio 10:1
• Horizontal: Right side 85° (typ.), Left side 85° (typ.)
• Vertical: Up side 85° (typ.), Down side 85° (typ.)
At DPS= Low or open: normal scan
• Viewing angle with optimum grayscale (γ=2.2): normal axis
Polarizer surface
Polarizer pencil-hardness
Clear
3H (minD.)a[tbaySJhIeSeKt45U4.0c0o]m
Color gamut
At LCD panel center
40 % (typ.) [against NTSC color space]
Response time
Ton (black 10% → white 90%)
24 ms (typ.)
Luminance
At 5.0mArms / lamp
350 cd/m2 (typ.)
Signal system
6-bit digital signals for data of RGB colors,
Dot clock (CLK), Data enable (DE),
Horizontal synchronous signal (Hsync),
Vertical synchronous signal (Vsync)
Power supply voltage
Backlight
LCD panel signal processing board: 3.3V or 5.0V
Edge light type: 2 cold cathode fluorescent lamps
Replaceable parts
• Lamp holder set: Type No. 104LHS39
Recommended inverter (Option)
• Inverter: Type No. 104PW191, 104PW161
Power consumption
At 5.0mArms / lamp and checkered flag pattern
6.2 W (typ.)
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PRELIMINARY DATA SHEET DOD-M- 1309 (2nd edition)
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NL6448BC33-53
4.4 POWER SUPPLY VOLTAGE SEQUENCE
4.4.1 Sequence for LCD panel signal processing board
VCC
Note1
3.0V or 4.75V
0V
Display and
function signals
Note2
ON
Tr < 30ms
0ms < t < 35ms
VALID period
OFF
Toff > 50ms
0ms < t < 35ms
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Note1: In terms of voltage variation (voltage drop) while VCC rising edge is below 3.0V in
"VCC = 3.3V" or 4.75V in "VCC = 5.0V", a protection circuit may work, and then this
product may not work.
Note2: Display (CLK, Hsync, Vsync, DE, R0 to R5, G0 to G5, B0 to B5) and function (DPS)
signals must be Low or High-impedance, exclude the VALID period (See above sequence
diagram), in order to avoid that internal circuits is damaged.
If some of display and fuDncattiaoSnhseiegtn4aUls.coofmthis product are cut while this product is
working, even if the signal input to it once again, it might not work normally. If customer
stops the display and function signals, they should be cut VCC.
4.4.2 Sequence for backlight inverter (Option)
Display and
function signals
Note1
Note2
VALID period
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VDDB
Note1: These are the display and function signals for LCD panel signal processing board.
Note2: The backlight inverter voltage (VDDB) should be inputted within the valid period of
display and function signals, in order to avoid unstable data display.
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PRELIMINARY DATA SHEET DOD-M- 1309 (2nd edition)
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