PDF M38857F Data sheet ( Hoja de datos )

Número de pieza	M38857F
Descripción	SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fabricantes	Renesas Technology
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No Preview Available ! www.DataSheet4U.com To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. DataSheet4U.com DataShee Renesas Technology Corp. Customer Support Dept. April 1, 2003 DataSheet4U.com DataSheet4 U .com DataSheet4U.com 1 page www.DataSheet4U.com Table 2 Pin description (2) Pin Name P40/XCOUT P41/XCIN P42/INT0 P43/INT1 P44/RxD P45/TxD P46/SCLK I/O port P4 P47/SRDY /CLKRUN P50/INT5 P51/INT20 P52/INT30 P53/INT40 P54/CNTR0 P55/CNTR1 I/O port P5 P56/DA1/PWM01 P57/DA2/PWM11 P60/AN0–P67/AN7 I/O port P6 et4U.com P70 P71 P72 P73/INT21 P74/INT31 P75/INT41 I/O port P7 P76/SDA P77/SCL P80/LAD0 P81/LAD1 P82/LAD2 P83/LAD3 P84/LFRAME P85/LRESET P86/LCLK P87/SERIRQ I/O port P8 MITSUBISHI MICROCOMPUTERS 3885 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Functions •8-bit I/O port with the same function as port P0 <Input level> CMOS compatible input level <Output level> P40, P41 : CMOS 3-state output structure P42-P47 : CMOS 3-state output structure or N- channel open-drain output structure •Each pin level of P42 to P46 can be read even in output port mode. •8-bit I/O port with the same function as port P0 •CMOS compatible input level •CMOS 3-state output structure Function except a port function •Sub-clock generating circuit I/O pins (Connect a resonator.) •Interrupt input pins •Serial I/O function pins •Serial I/O function pins •Serialized IRQ function pin •Interrupt input pins •Timer X, timer Y function pins •D-A converter output pins •PWM output pins •8-bit I/O port with the same function as port P0 •CMOS compatible input level. •A-D converter output pins •CMOS 3-state output structure. •8-bit CMOSDI/aOtapSorht eweitht4tUhe.csoamme function as port P0 <Input level> P70–P75 : CMOS compatible input level or TTL compatible input level P76, P77 : CMOS compatible input level or SMBUS input level in the I2C-BUS interface function, •Interrupt input pins <Output structure> N-channel open-drain output structure •I2C-BUS interface function pins •Each pin level of P70 to P75 can be read evev in output port mode. •8-bit CMOS I/O port with the same function as port P0 •CMOS compatible input level. •CMOS 3-state output structure. •LPC interface function pins DataShee •Serialized IRQ function pin DataSheet4U.com 4 DataSheet4U.com 5 Page www.DataSheet4U.com [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B16. MITSUBISHI MICROCOMPUTERS 3885 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 1 CPU mode register (CPUM : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Not available 1 0 : Not available 1 1 : Not available Stack page selection bit 0 : 0 page 1 : 1 page Fix this bit to “1”. Port P40/P41 switch bit 0 : I/O port function (stop oscillating) 1 : XCIN–XCOUT oscillating function Main clock (XIN–XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : φ = f(XIN)/2 (high-speed mode) 0 1 : φ = f(XIN)/8 (middle-speed mode) 1 0 : φ = f(XCIN)/2 (low-speed mode) 1 1 : Not available et4U.com Fig. 7 Structure of CPU mode register DataSheet4U.com DataShee DataSheet4U.com 10 DataSheet4U.com 11 Page

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