PDF UT54ACTS220 Data sheet ( Hoja de datos )

Número de pieza	UT54ACTS220
Descripción	Clock and Waut State Generation Circuit
Fabricantes	Aeroflex Microelectronic Solutions
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No Preview Available ! www.DataSheet4U.com UT54ACTS220 Clock and Wait-State Generation Circuit FEATURES • 1.2µ radiation-hardened CMOS PINOUTS - Latchup immune 14-Pin DIP • High speed Top View • Low power consumption • Single 5-volt supply • Available QML Q or V processes • Flexible package - 14-pin DIP - 14-lead flatpack NC 1 14 VDD CLKOUT 2 13 24MHz CLKOUT 3 12 DTACK CLKIN 4 11 TEST NC 5 10 MRST DESCRIPTION 48MHz 6 9 RCS The UT54ACTS220 is designed to be a companion chip to VSS 7 8 DMACK UTMC’s UT69151 SµMMIT family for the purpose of gener- ating clock and wait-state signals. The device contains a divide by two circuit that accepts TTL input levels and drives CMOS output buffers. The chip accepts a 48MHz clock and generates a 24MHz clock. The 48MHz clock can have a duty cycle that 14-Lead Flatpack Top View varies by ± 20%. The UT54ACT220 generates a 24MHz clock with a ± 5% duty cycle variation. The wait-state circuit generates NC a single wait-state by delaying the falling edge of DTACDKatianStoheet4U.cCoLmKOUT the SµMMIT. The clock/timing device generates DTACK from CLKOUT the falling edge of input RCS which is synchronized by the CLKIN falling edge of 24MHz. The SµMMIT drives inputs RCS and NC DMACK. 48MHz The devices are characterized over full military temperature VSS 1 14 2 13 3 12 4 11 5 10 69 78 range of -55°C to +125°C. LOGIC SYMBOL VDD 24MHz DTACK TEST MRST RCS DMACK DataShee MRST (10) S 48MHz (6) RCS (9) DMACK (8) CTR1 SRG2 1D S (13) 24MHz (12) DTACK (11) TEST (4) CLKIN (2) CLKOUT (3) CLKOUT Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. DataSheet4U.com 145 DataSheet4 U .com RadHard MSI Logic DataSheet4U.com 1 page www.DataSheet4U.com UT54ACTS220 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C) SYMBOL PARAMETER CONDITION VIL Low-level input voltage 1 TTL VIH High-level input voltage 1 TTL IIN Input leakage current TTL VDD = 5.5V VIN = VDD or VSS VOL1 Low-level output voltage 3 Except CLKOUT/CLKOUT IOL = 8mA, VDD = 4.5V IOL = 100µA VOH1 High-level output voltage 3 Except CLKOUT/CLKOUT IOH = -8mA, VDD = 4.5V VOL2 CLKOUT/CLKOUT Low-level output voltage 3 IOL = 100µA VOH2 CLKOUT/CLKOUT High-level output voltage 3 IOH = -100µA et4U.com IOS Short-circuit output current 2 ,4 VO = VDD and VSS VDD = 5.5V DataSheet4U.com IOL1 Output current10 VIN = VDD or VSS (Sink), Except CLKOUT/CLKOUT VOL = 0.4V IOH1 Output current10 (Source), Except CLKOUT/CLKOUT VIN = VDD or VSS VOH = VDD - 0.4V IOL2 CLKOUT/CLKOUT output current10 VIN = VDD or VSS (Sink) VOL = 0.4V IOH2 IIH IIL Ptotal CLKOUT/CLKOUT output current10 (Source) Input current high Input current low Power dissipation 2, 8, 9 VIN = VDD or VSS VOH = VDD - 0.4V VIN = VDD or VSS VIN = 5.5V VIN = VDD or VSS VIN = VSS CL = 50pF IDDQ Quiescent Supply Current VDD = 5.5V VIN = VDD or VSS MIN 2.25 -1 3.15 4.25 8 -8 12 -12 MAX 0.8 UNIT V V 1 µA 0.4 0.25 V 0.25 +300 V V V mA DataShee mA mA mA mA +1.0 µA -1.0 µA 1.0 mW/ MHz 10 µA DataSheet4U.com 149 DataSheet4 U .com RadHard MSI Logic DataSheet4U.com 5 Page

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