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PDF T8208 Data sheet ( Hoja de datos )

Número de pieza T8208
Descripción ATM Interconnect
Fabricantes Agere Systems 
Logotipo Agere Systems Logotipo



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No Preview Available ! T8208 Hoja de datos, Descripción, Manual

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Advance Data Sheet
September 2001
CelXpresTM T8208
ATM Interconnect
1 Product Overview
s Programmable priority for control/data cells trans-
mission onto cell bus
1.1 Features
s Microprocessor access to all headers of control
cell
s OC-12 data throughput on UTOPIA (16-bit)
(independently on RX and TX UTOPIA)
s Shared UTOPIA mode
s Ability to clear counters on read
s Simplified looping to any system device with a sin-
gle register programming
s UTOPIA Level 1 and 2 (8-bit/16-bit) cell-level
handshake interface (ATM or PHY layers)
s Multi-PHY (MPHY) operation
s UTOPIA clock sourcing with additional settings
s Programmable operations and maintenance and
resource management (OAM/RM) cell routing
s Programmable ATM layer supports up to 64 PHY
ports
s Support of multicast and broadcast cells per PHY
s Egress SDRAM buffer support to extend UTOPIA
s Optional monitoring of misrouted cells
output priority queues for 32K to 512K cells:
s Counters for dropped cells per queue
— 128 queues configurable up to four queues per
PHY with programmable sizes
s Digital loopback before cell bus
DataShee
— Programmable number of UTOPIA output
s Microprocessor interface, supporting both Motor-
queues with four levels of priority DataSheet4U.com ola® and Intel® modes (multiplexed and nonmulti-
s Support of ATM traffic management via partial
plexed)
packet discard (PPD), forward explicit congestion s Control cell transmission and reception through
notification (FECN), and the cell loss priority (CLP)
microprocessor port
bit s Single 3.3 V power supply
s Programmable slew rate GTL+ I/O:
— Programmable as bus arbiter
— 1.7 Gbits/s cell bus operation
s 3.3 V TTL I/O (5 V tolerant)
s 272-pin plastic ball grid array (PBGA) package
s Flexible per port cell counters
s Cell header insertion with virtual path identifier
(VPI) and virtual channel identifier (VCI) translation
via external SRAM (up to 64K entries)
s Support of network node interface (NNI) and user
network interface (UNI) header types with optional
generic flow-control (GFC) insertion
s Industrial temperature range (–40 °C to +85 °C)
s Hot insertion capability
s Eight GPIO pins
s JTAG support
s Compatible with Transwitch CellBus®
s Optional sourcing of cell bus clocks from device
s LUT bypass option
1.2 Applications
s TX UTOPIA cell buffer increased to 256 cells for
better queue management with SDRAM queue
bypass option
s Ability for cell bus arbiter to mask devices on the
cell bus
s Ability to modify cell bus priority based on RX PHY
FIFO thresholds
s Asymmetric digital subscriber line (ADSL) digital
subscriber line access multiplexers (DSLAMs)
s Access gateways
s Access multiplexers/concentrators
s Multiservice platforms
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T8208 pdf
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Advance Data Sheet
September 2001
CelXpres T8208
ATM Interconnect
List of Tables
Table
Page
et4U.com
Table 1. UTOPIA Pins .............................................................................................................................................. 14
Table 2. Shared UTOPIA Pins .................................................................................................................................. 15
Table 3. Cell Bus Pins .............................................................................................................................................. 16
Table 4. SDRAM Interface Pins ................................................................................................................................ 17
Table 5. Microprocessor Interface Pins .................................................................................................................... 18
Table 6. Translation SRAM Interface ......................................................................................................................... 19
Table 7. JTAG Pins ................................................................................................................................................... 19
Table 8. General-Purpose Pins ................................................................................................................................ 20
Table 9. Power Pins .................................................................................................................................................. 20
Table 10. Loop Filter Register Settings ..................................................................................................................... 24
Table 11. Access Times ........................................................................................................................................... 27
Table 12. Active and Ignore Truth Table .................................................................................................................. 33
Table 13. VPI Value Truth Table .............................................................................................................................. 34
Table 14. OAM Routing Control Truth Table ............................................................................................................ 34
Table 15. F5 Translation Record Addresses Table—8-Byte Records ....................................................................... 35
Table 16. F5 Translation Record Addresses Table—Extended Mode ...................................................................... 41
Table 17. Pin Configuration for 8-Bit UTOPIA .......................................................................................................... 53
Table 18. Pin Configuration for 16-Bit UTOPIA ........................................................................................................ 57
Table 19. Supported Memory Configurations ........................................................................................................... 71
Table 20. Queue Organization and Port Group Address/Priority Bits for 32 Ports in 8-Bit UTOPIA Mode ............ 74
Table 21. Queue Organization and Port Group Address/Priority Bits for 64 Ports in 8-Bit UTOPIA Mode and
32 Ports in 16-Bit UTOPIA Mode .............................................................................................................. 77DataShee
Table 22. Instruction Register ................................................................................................................................... 84
Table 23. Boundary-Scan Register DescriptioDnasta..S..h..e..e..t.4..U.....c..o..m................................................................................. 85
Table 24. Register Map .............................................................................................................................................. 88
Table 25. Identification 0 (IDNT0) (00h) ................................................................................................................... 92
Table 26. Identification 1 (IDNT1) (01h) .................................................................................................................... 92
Table 27. Identification 2 (IDNT2) (02h) ................................................................................................................... 92
Table 28. Direct Configuration/Control Register (DCCR) (28h)................................................................................ 93
Table 29. Interrupt Service Request (ISREQ) (29h) ................................................................................................. 94
Table 30. mclk PLL Configuration 0 (MPLLCF0) (2Ah) ............................................................................................ 94
Table 31. mclk PLL Configuration 1 (MPLLCF1) (2Bh) ............................................................................................ 95
Table 32. GTL+ Slew Rate Configuration (GTLSRCF) (2Eh) .................................................................................... 95
Table 33. GTL+ Control (GTLCNTRL) (2Fh) ........................................................................................................... 96
Table 34. Extended Memory Address 1 (Little Endian) (EMA1_LE) (30h) ................................................................ 97
Table 35. Extended Memory Address 2 (Little Endian) (EMA2_LE) (31h) ................................................................ 97
Table 36. Extended Memory Address 3 (Little Endian) (EMA3_LE) (32h) ................................................................ 97
Table 37. Extended Memory Address 4 (Little Endian) (EMA4_LE) (33h) ................................................................ 97
Table 38. Extended Memory Access (Little Endian) (EMA_LE) (34h) ....................................................................... 97
Table 39. Extended Memory Data Low (Little Endian) (EMDL_LE) (36h) ................................................................. 98
Table 40. Extended Memory Data High (Little Endian) (EMDH_LE) (37h) ................................................................ 98
Table 41. Extended Memory Address 4 (Big Endian) (EMA4_BE) (30h) .................................................................. 99
Table 42. Extended Memory Address 3 (Big Endian) (EMA3_BE) (31h) .................................................................. 99
Table 43. Extended Memory Address 2 (Big Endian) (EMA2_BE) (32h) .................................................................. 99
Table 44. Extended Memory Address 1 (Big Endian) (EMA1_BE) (33h) .................................................................. 99
Table 45. Extended Memory Access (Big Endian) (EMA_BE) (34h) ....................................................................... 100
Table 46. Extended Memory Data High (Big Endian) (EMDH_BE) (36h) ................................................................ 100
Table 47. Extended Memory Data Low (Big Endian) (EMDL_BE) (37h) ................................................................. 100
Table 48. GPIO Output Enable (GPIO_OE) (39h) ................................................................................................... 101
Table 49. GPIO Output Value (GPIO_OV) (3Bh) .................................................................................................... 101
Table 50. GPIO Input Value (GPIO_IV) (3Dh) ......................................................................................................... 101
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T8208 arduino
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Advance Data Sheet
September 2001
CelXpres T8208
ATM Interconnect
1 Product Overview (continued)
Figure 2 illustrates the use of the CelXpres T8208 in a system with dual backplane cell buses using shared UTO-
PIA mode. In this configuration, both T8208 devices on each card receive cells from the UTOPIA bus, and each
device uses its translation table to determine if the cell should be transmitted on its backplane cell bus. In the
egress direction, each T8208 device receives cells from its cell bus to transmit on the UTOPIA bus. MPHY arbitra-
tion and queue priorities are resolved using a six-wire interface between the two devices. Although a single ATM
virtual connection is not typically established on both backplane cell buses simultaneously, no restrictions exist for
a single PHY utilizing both backplane cell buses for different virtual connections supporting higher throughput from
two bus interfaces. Redundant bus configurations can be supported in the event of a bus failure with T8208
devices by configuring one device to assume bus responsibility from the other.
et4U.com
DOWNSTREAM
UPSTREAM
BUFFERING
TRANSLATION
T8208
UTOPIA
T8208
UTOPIA
PHYs
DOWNSTREAM
UPSTREAM
BUFFERING
TRANSLATION
DOWNSTREAM
UPSTREAM
BUFFERING
TRANSLATION
BACKPLANE
BUS
T8208
DataSheet4U.com
UTOPIA
T8208
DOWNSTREAM
UPSTREAM
BUFFERING
TRANSLATION
UTOPIA
PHYs
Figure 2. Dual Bus Implementation
DataShee
0041b
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