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PDF UM6532A Data sheet ( Hoja de datos )

Número de pieza UM6532A
Descripción RAM / I/O / Timer Array
Fabricantes UMC 
Logotipo UMC Logotipo



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UM6532/ UM6532A
RAM, /10, Timer Array
Features
• 8 bit bi-directional Data Bus for direct communica-
·tion with the microprocessor
• Programmable edge-sensitive interrupt
• 128 x 8 static RAM
• Two 8 bit bi-directional data ports for interface to
peripherals
• Two programmable I/O peripheral data direction
registers
• Programmable interval timer
• Programmable interval timer interrupt
• Peripheral pins with direct transistor drive capability
• High impedance three-state data pins
General Description
The UM6532 is designed to operate in conjunction with
the UM6500 Microprocessor Family. It is comprised of a
128 x 8 static RAM, two software controlled ,8 bit bi-
directional data ports allowing direct interfacing between
the microprocessor unit and peripheral devices, a software
programmable interval timer with interrupt capable of
timing in various intervals from 1 to 262,144 clock periods,
and a programmable edge-detect interrupt circuit.
Pin Configuration
Block Diagram
vss A6
A5 r/J2
PAO PA7
PBO PB7
A4 eS1
A3 eS2
A2 RS
A1 R!W
AO RES
PAO 00
PA1 01
PA2 02
PA3 03
PA4 04
PA5 05
PA6 06
PA7 07
PB7 IRQ
PB6 PBO
PB5 PB1
PB4
Vee
PB2
PB3
DO D7
AO A6 AS CSl CS2 "'2 RtWliES
7-80

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UM6532A pdf
(lJUMC
RAM 128 Bytes (1024 Bits)
A 128 x 8 static RAM is contained on the UM6532. It is
addressed by AO-A6 (Byte Select), RS, CS1, and CS2.
Internal Peripheral Registers
There are four 8-bit internal registers: two data direction
registers and two output registers: The two data direction
registers (A side and B side) control the direction of the
data into and out of the peripheral I/O. A logic zero in a
bit of the data direction register (DDRA and DDR B) causes
the corresponding line of the I/O port to act as an input. A
logic one causes the corresponding line to act as an output.
The voltage on any line programmed as an output is deter~
mined by the corresponding bit in the output register
(ORA and ORB).
Data is read directly from the PA lines duringa peripheral
read operation. For a PA pin progrpmmed as an output,
the data transferred into the processor will be the same as
the data in the ORA only if the voltage on the line is
allowed to be ~ 2.4 volts for a logic one and ~ 0.4 volts for
a zero. If the loading on the line does not allow this, then
the data resulting from the read operation may not match
the contents of ORA.
The output buffers for the PB lines are somewhat different
from the PA buffers. The PB buffers are push-pull devices
which are capable' of sourcing 3 mA at 1.5 volts. This
allows these lines to directly drive transistor circuits. To
assure that the processor will read the proper data when
performing a peripheral read operation, logic is provided in
the peripheral B port to permit the processor to read the
contents of ORB, instead of the PB lines.
Interval Timer
The Timer section of the UM6532 contains three basic
parts: preliminary divide down register, programmable
Value read = 1 1 1 0 0 1 0 0
Complement = 0 0 0 1 1 0 1 1
Add 1
= 0 0 0 1 1 1 0 0 = 28.
UM6532/ UM6532A
8-bit register and interrupt logic. These are illustrated in
Figure 1.
The Interval Timer can be programmed to count up to 256
time intervals. Each time interval can be either H, 8T,
64T, or'1 024T increments, where T is' the system clock
period. When a full count is reached, the interrupt flag is
s~t to a logic "1". After the interrupt flag is set the internal
clock continues counting down, but at a 1T rate to a
maximum of-255T. This allows the user to read the
counter and then determine how long the interrupt has
been set.
The 8-bit system Data Bus is used to transfer data to and
from the Interval Timer. If a count of 52 time intervals
were to be counted, the pattern 0 0 1 1 0 1 0 0 would be
put on the Data Bus and written into the Interval Time
register.
At the same time that data is being written to the Interval
Timer, the counting intervals of 1, 8, 64, 1024T are
decoded from address lines AO and A 1. During a Read or
Write· operation address line A3 controls the interrupt
capability of IRQ, i.e., A3=1 enables IRQ, A3=0 disables
IRQ. In either case, when timeout occurs, bit 7 of the
Interrupt Flag Register is set. This flag is cleared when the
Timer register is either read from or written to by the
processor. If I RQ is enabled by A3 and an interrupt
occurs IRQ will go low. When the Timer is read prior to
the interrupt flag being set, the number of time intervals
remaining wil! be read, ie., 51. 50.49. etc.
When the Timer has counted down to 0 0 0 0 0 0 0 0 an
interrupt will occur on the next count time and the counter
will read 1 1 1 1 1 1 1J. After interrupt, the Timer register
decrements at a divide by "1" rate of the system clock. If
after interrupt, the Timer is read and a value of
1 1 1 0 0 1 0 0 is read, the time since interrupt is 28T. The
value read is in two's complement.
R/WPA7 A3
07 06 05 04 03 02 01 DO
R!W A1
AO
07 06
05 04 03 02 01 DO
Figure 1. Basic Elements of Interval Timer
7-84

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