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PDF UM6512 Data sheet ( Hoja de datos )

Número de pieza UM6512
Descripción (UM6502 - UM6512) 8-bit Microprocessor
Fabricantes UMC Corporation 
Logotipo UMC Corporation Logotipo



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No Preview Available ! UM6512 Hoja de datos, Descripción, Manual

EDUMC
UM6502/UM6507/UM6512
=====;::~==::=;i:: 8-Bit Microprocessors
Features
• Single 5V ± 5% power supply
• N channel, silicon gate, depletion load technology
• 56 instructions
• Decimal and binary arithmetic
• Thirteen addressing modes
• True indexing capability
• Programmable stack pointer
• Variable length stack
• Interrupt capability
• Non-maskable interrupt
• Bi-directional data bus
General Description
The UM6502/UM6507/UM6512 microprocessors are totally
software compatible with one another. These products
provide a selection of addressable memory range, interrupt
input options and on-chip clock oscillators and drivers.
The UM6502/UM6507 on-chip clock versions are aimed
at high performance, low cost applications where single
Pin Configuration
• Addressable memory range of up to 64K bytes
• "Ready" input
• Direct memory access capabilitv
• Bus compatible with MC6800
• Choice of external or on-board clocks
• 1MHz, 2MHz, 3MHz and 4MHl versions
• On-chip clock options
-External single clock input
-Crystal time base input
• Pipeline architecture
phase inputs or crystals provide the time base. The
UM6512 external clock version is geared for the multi-
processor system applications where maximum timing
control is mandatory. These products are bus compatible
with the MC6800 product offering.
Vss
ROY
CPl (OUT)
TAO
N. c.
NMT
SYNC
Vcc
ABO
ABl
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
ABll
RES
if>2 (OUT)
S. O.
if>o (IN)
N. c.
N. c.
R/IN
DBO
DBl
DB2
DB3
DB4
DB5
DB6
DB7
AB15
AB14
AB13
AB12
Vss
RES
Vss
ROY
Vcc
ABO
ABl
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
CP2 (OUT)
if>o (IN)
Riw
DBO
DBl
DB2
DB3
DB4
DB5
DB6
DB7
AB12
ABll
AB10
Vss
ROY
if> 1
IRQ
Vss
NMT
SYNC
Vcc
ABO
ABl
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
ABll
RES
if>2 (OUT)
S.O.
if>2
DBE
N. C.
R/W
DBO
DBl
DB2
DB3
DB4
DB5
DB6
DB7
AB15
AB14
AB13
AB12
Vss
4-3

1 page




UM6512 pdf
eUMC
Dynamic Operating Characteristics
(Vcc = 5.0 ± 5%, TA = 0° to 70°C)
UM6502/UM6507/UM6512
Parameter
Symbol
1 MHz
Min.
Max.
2MHz
Min.
Max.
3MHz
Min.
Max.
4MHz
Min.
Max.
Units
UM6512
Cycle Time
TCYC
1.00
40
0.50
40
0.33 . 40
0.25
40
<1>1 Pulse Width
TPWH<I> I
430
-
215 -
150 -
<1>2 Pulse With
Delay Between <1>1 and <1>2
TPWH<I>2
TD
470
0
-
-
235 -
0-
160 -
0-
<1>1 and <1>2 Rise and Fall Times(l)
TR. TF
0
25
0
20
0
15
J..IS
ns
ns
ns
ns
UM6502/UM6507
Cycle Time
<1>0 (I N) Low Time(2)
<1>0 (I N) High Time(2)
TCYC
1.00
40
0.50
40
0.33
40
0.25
40
Tut>o 480 -
240 -
160 -
110 -
THcPo 460 -
240 -
160 -
115 -
<1>0 Neg to'<I> 1 Pos Delay (5)
cPo Neg to <1>2 Neg Delay(5)
<1>0 Pos to cPl Neg Delay(5)
<1>0 Pos to cP2 Pos Delay(5)
T01+
10 70
10 70
10 70
10 70
T02- 5 65 5 65 5 65 5 65
T01- 5 65 5 65 5 65 5 65
T02+
15 75
15 75
15 75 15 75
. ¢O(IN) Rise and Fall Time(l)
TRO,TFO
0
30
0
20
0
15 0
10
<1>1 (OUT), Pulse Width
<1>2 (OUT). Pulse Width
Delay Between cP 1 and <1>2
<1>1 and <1>2 Rise and Fall Times(l, 3)
TpWH<I>1
TPWH<I>2
TO
TR, TF
TLcPo·20 TL<I>o TL<I>o·20 TL<I>o TL<I>o·20 TL<I>o TL¢o·20 TL<I>o
TLcPo·40 TL<I>o·10 TL<I>o·40 TL<I>o·40 TLcPoAO TLcPo· 10 TL<I>o·40 TL<I>o·10
5-
5-
5-
5-
- 25 -
25 -
15 -
15
J..IS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UM6502/U M6507 /U M6512
R/W Setup Time
R/W Hold Time
Address Setup Time
Address Hold Time
Read Access Time
Read Data Setup Time
Read Data Hold Time
Write Data Setup Time
Write Data Hold Time
Sync Setup Time
Sync Hold Time
RDY Setup Time(4)
TRWS
TRWH
TADS
TADH
TACC
TDSU
THR
TMDS
THW
TSYS
TSYH
TRS
- 225 -
140 -
110 -
90
30 -
30 -
15 -
10
- 225 -
140 -
110 -
-
90
30 -
30 -
15 -
10 -
- 650 - 310 -
170 -
110
100 -
50 - 50 -
50 -
10 -
10 -
10 -
10 -
20 175 20 100 20 75 -
60 150 60 150 30 130 20
- 350 -
175 -
100 -
70
-
90
30 -
30 -
15 -
15 -
200 -
200 -
150 -
120 -
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Measured between 10010 and 90% points.
2. Measured at 50% points.
3. Load = 1 TTL load + 30 pF.
4. RDY must never switch states with in T RS to end of <1>2'
5. Load = 100 pF.
6. The 2 MHz devices are identified by an "A" suffix.
7. The 3 MHz devices are identified by an "B" suffix.
8. The 4 MHz devices are identified by an '·'c" suffix.
Timing Diagram Note:
Because the clock generation for the UM6502/UM6507
and UM6512 is different. the two clock timing sections are
referenced to the main timing diagram by three reference
lines marked REF 'A', REF 'B' and REF 'C'. Reference
between the two sets of clock timings is without meaning.
Timing parameters are referred to these lines and scale
variations in the diagrams are of no consequence.
4-7

5 Page





UM6512 arduino
UM6502/UM6507/UM6512
Z Page. X
Abs. X
Abs. V
Relative
Indirect
Z Page. V
OP n # OP n # OP n # OP n # OP n # OP n #
75 4
35 4
16 6
2 70 4
2 3D 4
2 1E 7
3 79 4
3 39 4
3
3
3
90 7
BO 2
FO 2
30 2
DO 2
10 2
2
2
2
2
2
2
50 2 2
70 2 2
05 4 2 DO 4 3 09 4 3
06 6 2 DE 7 3
55 4 2 50 4 3 59 4 3
F6 6 2 FE 7 3
B5 4
B4 4
56 6
15 4
2 BD 4
2 BC 4
2 5E 7
2 10 4
3 B9 4
BE 4
3
3
3 19 4
3
3
3
6C 5 3
B6 4 2
36 6
76 6
2 3E 7
2 7E 7
3
3
F5 4 2 FD 4 3 F9 4 3
95 4
94 4
2 90 5
2
3 99 5
3
96 4 2
X INDEX X
Y INDEX Y
A ACCU MU LATO R
M MEMORY PER EFECTIVE ADDRESS
Ms MEMORY PER STACK POINTER
+ ADD
- SUBTRACT
1\ AND
V OR
V EXCLUSIVE OR
Processor Status Codes
7 6 54 3 2 1 0
Mnemonic
NV
B0 I Z C
NV
N
N
Z CA 0 C
CZ A N 0
Z ASL
BCC
BCS
M7 M6
B EQ
Z BIT
BM I
BN E
BP L
11
ci
BRK
BV C
6B V S
C LC
C L0
N6
N
N
0 CLI
Z CLV
CCMP
Z CCPX
Z CCPY
N Z 0 EC
N Z 0 EX
N Z 0 EY
N Z E0 R
N Z I NC
N Z I NX
N Z I NY
J MP
Z J SR
N L0 A
N Z L0 X
CN Z L 0 Y
0 Z L SR
Z N0 P
N 0 RA
PHA
N"
.Z
(RESTORED)
PHP
P LA
P LP
N Z CR0 L
N .... Z C R 0 R
(RESTORED)
RT I
NV
Z RTS
(3) S B C
; 1 SEC
S E0
1 SEI
STA
STX
N
Z STY
TAX
N Z TAY
N Z TSX
N Z TXS
TY S
N Z TYA
M7 MEMORY BIT 7
M6 MEMORY BIT 6
n NO. CYCLES
# NO. BYTES
Ordering Information
1 MHz
UM6502
UM6507
UM6512
2MHz
UM6502A
-
UM6512A
3MHz
UM6502B
-
UM6512B
4MHz
UM6502C
-
UM6512C
Part
Number
UM6502
UM6507
UM6512
Clocks Pins IRQ NMI RVO Addressing
On-Chip
On-Chip
External
40
28
40
..; ..;
..; ..;
.~.;
64K
8K
64K
4-13

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