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PDF IR3081 Data sheet ( Hoja de datos )
| Número de pieza | IR3081 | |
| Descripción | XPHASE VR 10.0 CONTROL IC | |
| Fabricantes | International Rectifier | |
| Logotipo |  |
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IR3081
DATA SHEET
XPHASETM VR 10.0 CONTROL IC
DESCRIPTION
The IR3081 Control IC combined with an IR XPhaseTM Phase IC provides a full featured and flexible way
to implement a complete VR 10.0 power solution. The “Control” IC provides overall system control and
interfaces with any number of “Phase ICs” which each drive and monitor a single phase of a multiphase
converter. The XPhaseTM architecture results in a power supply that is smaller, less expensive, and easier
to design while providing higher efficiency than conventional approaches.
The IR3081 is intended for VRD or VRM/EVRD 10.0 applications that use external VCCVID/VTT circuits.
FEATURES
• 6 bit VR 10.0 compatible VID with 0.5% overall system accuracy
• Programmable Dynamic VID Slew Rate
• No Discharge of output capacitors during Dynamic VID step-down (can be disabled)
• +/-300mV Differential Remote Sense
• Programmable 150kHz to 1MHz oscillator
• Programmable VID Offset and Load Line output impedance
• Programmable Softstart
• Programmable Hiccup Over-Current Protection with Delay to prevent false triggering
• Simplified Powergood provides indicDaatitoanSohfepert4oUpe.croomperation and avoids false triggering
• Operates from 12V input with 9.1V Under-Voltage Lockout
• 6.8V/5mA Bias Regulator provides System Reference Voltage
• Enable Input
• Small thermally enhanced 28L MLPQ package
DataShee
PACKAGE PINOUT
1 OSCDS
2 VID5
3 VID0
4 VID1
5 VID2
6 VID3
7 VID4
IR3081
CONTROL
IC
VBIAS
BBFB
EAOUT
FB
VDRP
IIN
OCSET
21
20
19
18
17
16
15
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IR3081
PIN DESCRIPTION
et4U.com
PIN# PIN SYMBOL
1 OSCDS
2-7
8, 9,
11,12
10
13
VID0-5
TRM1-4
VOSNS-
ROSC
14 VDAC
15 OCSET
16 IIN
17 VDRP
18 FB
19 EAOUT
20 BBFB
21 VBIAS
22 VCC
23 LGND
24 RMPOUT
25 SS/DEL
26 PWRGD
27 N/C
28 ENABLE
PIN DESCRIPTION
Apply a voltage greater than VBIAS to disable the oscillator. Used during factory
testing & trimming. Ground or leave open for normal operation.
Inputs to VID D to A Converter
Used for precision post-package trimming of the VDAC voltage. Do not make any
connection to these pins.
Remote Sense Input. Connect to ground at the Load.
Connect a resistor to VOSNS- to program oscillator frequency and FB, OCSET,
BBFB, and VDAC bias currents
Regulated voltage programmed by the VID inputs. Current Sensing and PWM
operation are referenced to this pin. Connect an external RC network to VOSNS- to
program Dynamic VID slew rate.
Programs the hiccup over-current threshold through an external resistor tied to
VDAC and an internal current source. Over-current protection can be disabled by
connecting this pin to a DC voltage no greater than 6.5V (do not float this pin as
improper operation will occur).
Current Sense input from the Phase IC(s). To ensure proper operation bias to at
least 250mV (don’t float this pin).
Buffered IIN signalD. CatoanSnheecetta4nU.ecxotmernal RC network to FB to program converter
output impedance
Inverting input to the Error Amplifier. Converter output voltage is offset from the
VDAC voltage through an external resistor connected to the converter output voltage
at the load and an internal current source.
Output of the Error Amplifier
Input to the Regulation Detect Comparator. Connect to converter output voltage and
VDRP pin through resistor network to program recovery from VID step-down.
Connect to ground to disable Body BrakingTM during transition to a lower VID code.
6.8V/5mA Regulated output used as a system reference voltage for internal circuitry
and the Phase ICs.
Power for internal circuitry
Local Ground and IC substrate connection
Oscillator Output voltage. Used by Phase ICs to program Phase Delay
Controls Converter Softstart, Power Good, and Over-Current Timing. Connect an
external capacitor to LGND to program the timing. An optional resistor can be added
in series with the capacitor to program the over-current delay time.
Open Collector output that drives low during Softstart and any external fault
condition. Connect external pull-up.
No internal connection
Enable Input. A logic low applied to this pin puts the IC into Fault mode.
DataShee
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IR3081
IR3081 THEORY OF OPERATION
Block Diagram
et4U.com
The Block diagram of the IR3081 is shown in figure 6 and discussed in the following section.
VCC
ENABLE
+
9.1V
8.9V -
-
START
STOP
+ VCC
UVLO
COMPARATOR
ENABLE
-
START
COMPARATOR
S+TOP
+
-
IDISCHG
6uA
VCHG
4V
ON
0.2V
90mV
SS/DEL
DISCHARGE
DISCHARGE
COMPARATOR
-
+
DELAY
COMPARATOR
1.3V
OVER
CURRENT
FAULT
LATCH
S
R
OC
COMPARATOR
SS/DEL
ICHG
66uA
OFF
SOFTSTART
CLAMP
DataSheet4U.com
-
+ VDRP
AMP
DISABLE
ERROR
AMP
VID5
VID0
VID1
VID2
VID3
VID4
BBFB
VOSNS-
VBIAS
RMPOUT
ROSC
IROSC
IRIORSOCSC
IROSC
VID
IRCOOSNCTROL
IROSC
IROSC
IROISRCOSC
VID = 11111X
VID STEP-DOWN
VID DAC OUTPUT
50%
DUTY
CYCLE
RAMP GENERATOR
5.0V
1.0V
VBIAS
IROSC
IOCSETIROSC
0.6V
+
-
+
1.2V
-
VBIAS
REGULATOR
CURRENT
SOURCE
GENERATOR
ROSC
BUFFER
AMP
+
6.8V
-
IROSC IFB
Figure 6 – IR3081 Block Diagram
PWRGD
VDRP
IIN
OCSET
EAOUT
FB
DataShee
VDAC
LGND
VID Control
A 6-bit VID voltage compatible with VR 10.0, as shown in Table 1 is available at the VDAC pin. A detailed block
diagram of the VID control circuitry can be found in Figure 7. The VID pins are require an external bias voltage and
should not be floated. The VID input comparators, with 0.6V reference, monitor the VID pins and control the 6 bit
Digital-to-Analog Converter (DAC) whose output is sent to the VDAC buffer amplifier. The output of the buffer amp
is the VDAC pin. The VDAC voltage is post-package trimmed to compensate for the input offsets of the Error Amp
to provide a 1.0% system accuracy. The actual VDAC voltage does not determine the system accuracy and has a
DataSheet4Uw.icdoemr tolerance.
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| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet IR3081.PDF ] | |
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